Home
last modified time | relevance | path

Searched +full:db0 +full:- +full:db7 (Results 1 – 6 of 6) sorted by relevance

/linux/arch/x86/include/asm/
H A Ddebugreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 asm("mov %%db0, %0" :"=r" (val)); in native_get_debugreg()
46 * Apply __FORCE_ORDER to DR7 reads to forbid re-ordering them in native_get_debugreg()
50 * when running under SEV-ES. Taking a #VC exception is not a in native_get_debugreg()
52 * re-ordering might place the access into an unsafe location. in native_get_debugreg()
55 * re-ordered to happen before the call to sev_es_ist_enter(), in native_get_debugreg()
58 asm volatile("mov %%db7, %0" : "=r" (val) : __FORCE_ORDER); in native_get_debugreg()
70 asm("mov %0, %%db0" ::"r" (value)); in native_set_debugreg()
86 * Apply __FORCE_ORDER to DR7 writes to forbid re-ordering them in native_set_debugreg()
94 asm volatile("mov %0, %%db7" ::"r" (value), __FORCE_ORDER); in native_set_debugreg()
[all …]
/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
29 - maxItems: 4
30 - maxItems: 8
[all …]
/linux/arch/sh/boards/mach-migor/
H A Dlcd_qvga.c1 // SPDX-License-Identifier: GPL-2.0
23 * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?)
24 * Driver IC. This IC is connected to the SH7722 built-in LCDC using a
25 * SYS-80 interface configured in 16 bit mode.
38 /* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */
53 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data)); in write_reg()
60 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); in write_reg16()
61 sys_ops->write_data(sys_ops_handle, adjust_reg18(data)); in write_reg16()
70 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); in read_reg16()
71 data = sys_ops->read_data(sys_ops_handle); in read_reg16()
[all …]
/linux/arch/x86/include/asm/xen/
H A Dinterface.h2 * arch-x86_32.h
24 * Copyright (c) 2004-2006, K A Fraser
104 #define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT)
106 /* Maximum number of virtual CPUs in multi-processor guests. */
114 * start of the GDT because some stupid OSes export hard-coded selector values
115 * in their ABI. These hard-coded values are always near the start of the GDT,
135 #define TI_GET_DPL(_ti) ((_ti)->flags & 3)
136 #define TI_GET_IF(_ti) ((_ti)->flags & 4)
137 #define TI_SET_DPL(_ti, _dpl) ((_ti)->flags |= (_dpl))
138 #define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2))
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_hdmi.c3 * Copyright © 2006-2009 Intel Corporation
44 #include <media/cec-notifier.h>
76 drm_WARN(display->drm, in assert_hdmi_port_disabled()
77 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
85 drm_WARN(display->drm, in assert_hdmi_transcoder_func_disabled()
219 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
270 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in g4x_infoframes_enabled()
284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_write_infoframe()
285 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_write_infoframe()
289 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in ibx_write_infoframe()
[all …]
/linux/drivers/scsi/
H A DFlashPoint.c3 FlashPoint.c -- FlashPoint SCCB Manager for Linux
11 Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
14 and a BSD-style copyright; see LICENSE.FlashPoint for details.
229 unsigned char niSysConf; /* Adapter Configuration byte -
231 unsigned char niScsiConf; /* SCSI Configuration byte -
233 unsigned char niScamConf; /* SCAM Configuration byte -
235 unsigned char niAdapId; /* Host Adapter ID -
276 #define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */
278 #define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */
409 #define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */
[all …]