Searched full:cyclone5 (Results 1 – 14 of 14) sorted by relevance
| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | altera.yaml | 43 - altr,socfpga-cyclone5-socdk
51 - terasic,socfpga-cyclone5-sockit
52 - const: altr,socfpga-cyclone5
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | altr,socfpga-stmmac.yaml | 14 Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
126 On Cyclone5/Arria5, the register shift represents the PHY mode
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| /linux/arch/arm/boot/dts/intel/socfpga/ |
| H A D | socfpga_cyclone5_sockit.dts | 10 compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_mcv.dtsi | 10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_socrates.dts | 10 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_de10nano.dts | 15 compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_chameleon96.dts | 14 compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_de0_nano_soc.dts | 10 compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_sodia.dts | 12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_vining_fpga.dts | 12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
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| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | altr,rst-mgr.yaml | 15 - description: Cyclone5/Arria5/Arria10
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| /linux/Documentation/devicetree/bindings/arm/altera/ |
| H A D | socfpga-clk-manager.yaml | 14 tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
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| /linux/drivers/edac/ |
| H A D | altera_edac.h | 197 /******* Cyclone5 and Arria5 Defines *******/
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| H A D | altera_edac.c | 1726 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
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