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/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
H A D	cache.json	69 "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", 72 "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." 75 "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.", 78 "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle." 93 "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.", 96 "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle." 123 "PublicDescription": "This event counts energy consumption per cycle of L2 cache.", 126 "BriefDescription": "This event counts energy consumption per cycle of L2 cache."
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A D	stall.json	4 …"BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no oper… 8 …"BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no oper… 12 …"BriefDescription": "This event counts every cycle that no instruction was dispatched from decode … 16 …"BriefDescription": "This event counts every cycle that no instruction was dispatched from decode … 20 …"BriefDescription": "This event counts every cycle that no instruction was dispatched from decode … 24 …"BriefDescription": "This event counts every cycle that no instruction or operation Slot was dispa… 28 …"BriefDescription": "This event counts every cycle that no instruction was dispatched from decode … 32 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when no instructions … 36 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there i… 40 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there i… [all …]
H A D	cycle_accounting.json	5 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 10 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 15 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 20 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 25 …"BriefDescription": "This event counts every cycle that no instruction was committed due to the la… 40 …"BriefDescription": "This event counts every cycle that no instruction was committed and the oldes… 45 …"BriefDescription": "This event counts every cycle that no instruction was committed and the oldes… 50 …"BriefDescription": "This event counts every cycle that no instruction was committed and the oldes… 55 …"BriefDescription": "This event counts every cycle that no instruction was committed because the C… 60 …"BriefDescription": "This event counts every cycle that no instruction was committed because the C… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	9 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt… 12 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt… 15 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt… 18 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt… 21 …tion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empt… 24 …tion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empt… 27 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal… 30 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal… 33 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal… 36 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal… [all …]
/linux/include/linux/
H A D	timecounter.h	19 * Depending on which hardware it reads, the cycle counter may wrap 23 * @read: returns the current cycle value 27 * @mult: cycle to nanosecond multiplier 28 * @shift: cycle to nanosecond divisor (power of two) 40 * cycle counter wrap around. Initialize with 41 * timecounter_init(). Also used to convert cycle counts into the 44 * cycle counter hardware, locking issues and reading the time 45 * more often than the cycle counter wraps around. The nanosecond 48 * @cc: the cycle counter used by this instance 49 * @cycle_last: most recent cycle counter value seen by [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	21 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc… 24 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc… 27 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr… 30 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr… 39 …No operation issued due to the backend interlock. This event counts every cycle where the issue of… 42 …No operation issued due to the backend interlock. This event counts every cycle where the issue of… 45 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of… 48 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of… 51 …, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a s… 54 …, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a s… [all …]
/linux/drivers/staging/vme_user/
H A D	vme_fake.c	49 u32 cycle; member 57 u32 cycle; member 156 dma_addr_t buf_base, u32 aspace, u32 cycle) in fake_slave_set() argument 213 bridge->slaves[i].cycle = cycle; in fake_slave_set() 225 dma_addr_t buf_base, u32 aspace, u32 cycle) in fake_slave_get() argument 241 cycle = bridge->slaves[i].cycle; in fake_slave_get() 253 u32 aspace, u32 cycle, u32 dwidth) in fake_master_set() argument 321 bridge->masters[i].cycle = cycle; in fake_master_set() 339 u32 aspace, u32 cycle, u32 dwidth) in __fake_master_get() argument 352 cycle = bridge->masters[i].cycle; in __fake_master_get() [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	floating-point.json	6 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 13 …X, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. Th… 20 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 27 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 34 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 40 …ent. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to… 46 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov… 52 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov… 58 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov… 64 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov…
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	floating-point.json	6 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 13 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 20 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 27 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 34 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 41 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 48 …X, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. Th… 55 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 62 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 69 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… [all …]
/linux/drivers/ata/
H A D	libata-pata-timings.c	70 q->cycle = EZ(t->cycle, T); in ata_timing_quantize() 92 m->cycle = max(a->cycle, b->cycle); in ata_timing_merge() 133 * PIO/MW_DMA cycle timing. in ata_timing_compute() 141 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; in ata_timing_compute() 144 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; in ata_timing_compute() 146 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; in ata_timing_compute() 160 * DMA cycle timing is slower/equal than the fastest PIO timing. in ata_timing_compute() 169 * Lengthen active & recovery time so that cycle time is correct. in ata_timing_compute() 177 if (t->active + t->recover < t->cycle) { in ata_timing_compute() 178 t->active += (t->cycle - (t->active + t->recover)) / 2; in ata_timing_compute() [all …]
/linux/scripts/
H A D	headerdep.pl	`114 # $cycle[n] includes $cycle[n + 1]; 115 # $cycle[-1] will be the culprit 116 my $cycle = shift; 119 for my $i (0 .. $#$cycle - 1) { 120 $cycle->[$i]->[0] = $cycle->[$i + 1]->[0]; 122 $cycle->[-1]->[0] = 0; 124 my $first = shift @$cycle; 125 my $last = pop @$cycle; 130 for my $header (reverse @$cycle) { 141 # Find and print the smallest cycle starting in the specified node. [all …]`
/linux/arch/alpha/lib/
H A D	ev6-csum_ipv6_magic.S	36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence) 116 cmpult $20,$3,$3 # E : (1 cycle stall on $20) 117 addq $20,$18,$20 # E : U L U L (1 cycle stall on $20) 120 addq $20,$19,$20 # E : (1 cycle stall on $20) 125 addq $18,$19,$18 # E : (1 cycle stall on $19) 128 /* (1 cycle stall on $18, 2 cycles on $20) */ 131 zapnot $0,15,$1 # U : Start folding output (1 cycle stall on $0) 133 srl $0,32,$0 # U : U L U L : (1 cycle stall on $0) 136 extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1) 137 zapnot $1,3,$0 # U : ushort[0] (1 cycle stall on $1) [all …]
/linux/drivers/net/dsa/sja1105/
H A D	sja1105_tas.c	88 dev_dbg(ds->dev, "longest cycle time %lld ns\n", max_cycle_time); in sja1105_tas_set_runtime_params() 101 * iterate cyclically through the "schedule". Each "cycle" has an entry point 103 * hardware calls each cycle a "subschedule". 105 * Subschedule (cycle) i starts when 123 * \|cycle 0\|cycle 1\| 151 * - cycle 0: iterates the schedule table from 0 to 2 (and back) 152 * - cycle 1: iterates the schedule table from 3 to 5 (and back) 174 int cycle = 0; in sja1105_init_scheduling() local 300 schedule_entry_points[cycle].subschindx = cycle; in sja1105_init_scheduling() 301 schedule_entry_points[cycle].delta = entry_point_delta; in sja1105_init_scheduling() [all …]
/linux/Documentation/devicetree/bindings/regulator/
H A D	pwm-regulator.yaml	19 duty-cycle values must be provided via DT. Limitations are that the 21 Intermediary duty-cycle values which would normally allow finer grained 29 appropriate duty-cycle values. This allows for a much more fine grained 31 make an assumption that a %50 duty-cycle value will cause the regulator 49 description: Voltage and Duty-Cycle table. 54 - description: duty-cycle in percent (%) 63 Integer value encoding the duty cycle unit. If not 75 Duty cycle values are expressed in pwm-dutycycle-unit. 104 * Inverted PWM logic, and the duty cycle range is limited 119 /* Voltage Duty-Cycle */
/linux/tools/testing/selftests/tc-testing/tc-tests/actions/
H A D	gate.json	58 "name": "Add gate action with cycle-time", 74 …"cmdUnderTest": "$TC action add action gate cycle-time 200000000000ns sched-entry close 100000000n… 77 "matchPattern": "action order [0-9]: .cycle-time 200s.index 1000 ref", 85 "name": "Add gate action with cycle-time-ext", 101 …"cmdUnderTest": "$TC action add action gate cycle-time-ext 20000000000ns sched-entry close 1000000… 104 "matchPattern": "action order [0-9]: .cycle-time-ext 20s.index 1000 ref", 227 …"$TC action add action gate cycle-time 600000000000ns sched-entry open 600000000ns -1 8000000b ind… 228 … "$TC action add action gate cycle-time-ext 400000000000ns sched-entry close 100000000ns index 103" 257 …"$TC action add action gate cycle-time 600000000000ns sched-entry open 600000000ns -1 8000000b ind… 258 … "$TC action add action gate cycle-time-ext 400000000000ns sched-entry close 100000000ns index 103" [all …]
/linux/drivers/pwm/
H A D	pwm-sl28cpld.c	25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0. 30 * - The duty cycle will switch immediately and not after a complete cycle. 60 * We calculate the duty cycle like this: 129 unsigned int cycle, prescaler; in sl28cpld_pwm_apply() local 152 cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle); in sl28cpld_pwm_apply() 153 cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)); in sl28cpld_pwm_apply() 157 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't in sl28cpld_pwm_apply() 163 if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) { in sl28cpld_pwm_apply() 166 cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1); in sl28cpld_pwm_apply() 171 * we have a valid duty cycle for the new mode. in sl28cpld_pwm_apply() [all …]
H A D	pwm-ntxec.c	16 * - The period and duty cycle can't be changed together in one atomic action. 44 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are 62 * Changes to the period and duty cycle take effect as soon as the in ntxec_pwm_set_raw_period_and_duty_cycle() 65 * duty cycle is fully written. If, in such a case, the old duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle() 68 * To minimize the time between the changes to period and duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle() 99 * Writing a duty cycle of zero puts the device into a state where in ntxec_pwm_apply() 100 * writing a higher duty cycle doesn't result in the brightness that it in ntxec_pwm_apply() 103 * As a workaround, write ENABLE=0 when the duty cycle is zero. in ntxec_pwm_apply() 104 * The case that something has previously set the duty cycle to zero in ntxec_pwm_apply()
/linux/Documentation/hwmon/
H A D	dme1737.rst	167 cycle) of the input. The chip adjusts the sampling rate based on this value. 178 manual mode, the fan speed is set by writing the duty-cycle value to the 180 current duty-cycle as set by the fan controller in the chip. All PWM outputs 198 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%) 199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle 200 pwm[1-3]_auto_pwm_min min-speed duty-cycle 208 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm 211 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min 214 duty-cycle. If any of the temperatures rise above the auto_point3_temp value, 215 all PWM outputs are set to 100% duty-cycle. [all …]
H A D	vt1211.rst	194 PWM Auto Point PWM Output Duty-Cycle 196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255) 197 pwm[1-2]_auto_point3_pwm high speed duty-cycle 198 pwm[1-2]_auto_point2_pwm low speed duty-cycle 199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0) 212 PWM output duty-cycle based on the input temperature: 215 Thermal Threshold Output Duty-Cycle Output Duty-Cycle 218 - full speed duty-cycle full speed duty-cycle 220 - high speed duty-cycle full speed duty-cycle 222 - low speed duty-cycle high speed duty-cycle [all …]
/linux/Documentation/admin-guide/perf/
H A D	alibaba_pmu.rst	`26 - Group 0: PMU Cycle Counter. This group has one pair of counters 27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count 61 -e ali_drw_21000/cycle/ \ 65 -e ali_drw_21080/cycle/ \ 69 -e ali_drw_23000/cycle/ \ 73 -e ali_drw_23080/cycle/ \ 77 -e ali_drw_25000/cycle/ \ 81 -e ali_drw_25080/cycle/ \ 85 -e ali_drw_27000/cycle/ \ 89 -e ali_drw_27080/cycle/ -- sleep 10`
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	floating-point.json	49 …tion": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", 53 …ion": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", 58 …tion": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", 62 …ion": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", 67 …tion": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", 76 …tion": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", 80 …ion": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", 85 …"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB… 135 … "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", 144 … "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	floating-point.json	49 …tion": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", 53 …ion": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", 58 …tion": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", 62 …ion": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", 67 …tion": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", 76 …tion": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", 80 …ion": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", 85 …"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB… 135 … "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", 144 … "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
/linux/sound/firewire/
H A D	amdtp-stream.c	231 // of syt interval. This comes from the interval of isoc cycle. As 1394 in amdtp_stream_add_pcm_hw_constraints() 484 static unsigned int compute_syt_offset(unsigned int syt, unsigned int cycle, in compute_syt_offset() argument 487 unsigned int cycle_lo = (cycle % CYCLES_PER_SECOND) & 0x0f; in compute_syt_offset() 534 dst->syt_offset = compute_syt_offset(src->syt, src->cycle, transfer_delay); in cache_seq() 705 static void build_it_pkt_header(struct amdtp_stream s, unsigned int cycle, in build_it_pkt_header() argument 725 trace_amdtp_packet(s, cycle, cip_header, payload_length + header_length, data_blocks, in build_it_pkt_header() 828 static int parse_ir_ctx_header(struct amdtp_stream s, unsigned int cycle, in parse_ir_ctx_header() argument 863 // Handle the cycle so that empty packet arrives. in parse_ir_ctx_header() 877 trace_amdtp_packet(s, cycle, cip_header, payload_length, *data_blocks, in parse_ir_ctx_header() 897 static inline u32 increment_ohci_cycle_count(u32 cycle, unsigne argument 930 u32 cycle = compute_ohci_cycle_count(ctx_header_tstamp); compute_ohci_it_cycle() local 951 unsigned int cycle; generate_tx_packet_descs() local 1019 compute_syt(unsigned int syt_offset,unsigned int cycle,unsigned int transfer_delay) compute_syt() argument 1249 unsigned int cycle; skip_rx_packets() local 1294 unsigned int cycle = compute_ohci_it_cycle(ctx_header[offset], queue_size); process_rx_packets_intermediately() local 1384 unsigned int cycle; drop_tx_packets() local 1423 unsigned int cycle = compute_ohci_cycle_count(ctx_header[1]); process_tx_packets_intermediately() local 1519 unsigned int cycle = UINT_MAX; drop_tx_packets_initially() local 1630 unsigned int cycle = s->next_cycle; irq_target_callback_skip() local [all...]
/linux/Documentation/devicetree/bindings/input/
H A D	pwm-vibrator.yaml	`14 strength increases based on the duty cycle of the enable PWM channel 15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration). 18 driven at fixed duty cycle. If available this is can be used to increase 39 direction-duty-cycle-ns: 41 Duty cycle of the direction PWM channel in nanoseconds, 58 direction-duty-cycle-ns = <1000000000>;`

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