| /linux/Documentation/devicetree/bindings/tpm/ |
| H A D | google,cr50.yaml | 4 $id: http://devicetree.org/schemas/tpm/google,cr50.yaml#
7 title: Google Security Chip H1 (running Cr50 firmware)
14 One member is the H1 built into Chromebooks and running Cr50 firmware:
24 const: google,cr50
47 compatible = "google,cr50";
59 compatible = "google,cr50";
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| /linux/drivers/char/tpm/ |
| H A D | tpm_tis_spi_cr50.c | 6 * with Cr50 firmware.
22 * Cr50 timing constants:
61 * The cr50 interrupt handler just signals waiting threads that the
76 * Cr50 needs to have at least some delay between consecutive
86 * Note: There is a small chance, if Cr50 is not accessed in a few days, in cr50_ensure_access_delay()
116 * Cr50 might go to sleep if there is no SPI activity for some time and
123 * Note: There is a small chance, if Cr50 is not accessed in a few days, in cr50_needs_waking()
151 /* Reset the time when we need to wake Cr50 again */ in cr50_wake_if_needed()
156 * Flow control: clock the bus and wait for cr50 to set LSB before
158 * the last byte of header, but cr50 never does that in practice,
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| H A D | tpm_tis_i2c_cr50.c | 7 * cr50 is a firmware for H1 secure modules that requires special
60 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler.
64 * The cr50 interrupt handler signals waiting threads that the
364 * tpm_cr50_i2c_tis_status() - Read cr50 tis status.
367 * cr50 requires all 4 bytes of status register to be read.
386 * cr50 requires all 4 bytes of status register to be written.
403 * cr50 uses bytes 3:2 of status register for burst count and
665 { .compatible = "google,cr50", },
699 /* cr50 is a TPM 2.0 chip */ in tpm_cr50_i2c_probe()
751 vendor == TPM_TI50_I2C_DID_VID ? "ti50" : "cr50", in tpm_cr50_i2c_probe()
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| H A D | Kconfig | 85 bool "Cr50 SPI Interface"
88 If you have a H1 secure module running Cr50 firmware on SPI bus,
116 tristate "TPM Interface Specification 2.0 Interface (I2C - CR50)"
119 This is a driver for the Google cr50 I2C TPM interface which is a
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| H A D | tpm_tis_spi_main.c | 326 { "cr50", (unsigned long)cr50_spi_probe },
336 { .compatible = "google,cr50", .data = cr50_spi_probe },
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | sc7280-idp-ec-h1.dtsi | 71 cr50: tpm@0 { label
72 compatible = "google,cr50";
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| H A D | sc7180-trogdor.dtsi | 692 cr50: tpm@0 { label
693 compatible = "google,cr50";
1040 bias-disable; /* Rely on Cr50 internal pulldown */
1044 bias-disable; /* Rely on Cr50 internal pulldown */
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| H A D | sdm845-cheza.dtsi | 834 compatible = "google,cr50";
1016 bias-disable; /* Rely on Cr50 internal pulldown */
1020 bias-disable; /* Rely on Cr50 internal pulldown */
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| H A D | sc7280-herobrine.dtsi | 444 compatible = "google,cr50";
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3399-gru-bob.dts | 74 compatible = "google,cr50";
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| H A D | rk3399-gru-scarlet.dtsi | 709 compatible = "google,cr50";
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| /linux/drivers/video/fbdev/savage/ |
| H A D | savagefb_driver.c | 591 reg->CR50 = vga_in8(0x3d5, par); in savage_get_default_par()
744 vga_out8(0x3d5, reg->CR50, par); in savage_set_default_par()
1151 reg->CR50 = 0; in savagefb_decode_var()
1153 reg->CR50 = 0x10; in savagefb_decode_var()
1155 reg->CR50 = 0x30; in savagefb_decode_var()
1158 reg->CR50 |= 0x40; in savagefb_decode_var()
1160 reg->CR50 |= 0x80; in savagefb_decode_var()
1162 reg->CR50 |= 0x00; in savagefb_decode_var()
1164 reg->CR50 |= 0x01; in savagefb_decode_var()
1166 reg->CR50 |= 0xc0; in savagefb_decode_var()
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| H A D | savagefb.h | 167 unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; member
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| /linux/drivers/video/fbdev/via/ |
| H A D | share.h | 154 #define CR50 0x50 macro
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8195-cherry.dtsi | 458 compatible = "google,cr50";
806 cr50_int: cr50-irq-default-pins {
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| H A D | mt8192-asurada.dtsi | 937 cr50_int: cr50-irq-default-pins {
1404 compatible = "google,cr50";
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| H A D | mt8183-kukui.dtsi | 869 compatible = "google,cr50";
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| H A D | mt8186-corsola.dtsi | 1670 compatible = "google,cr50";
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