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/freebsd/contrib/opencsd/decoder/source/
H A Dtrc_core_arch_map.cpp44 { "Cortex-A77", { ARCH_V8r3, profile_CortexA } },
45 { "Cortex-A76", { ARCH_V8r3, profile_CortexA } },
46 { "Cortex-A75", { ARCH_V8r3, profile_CortexA } },
47 { "Cortex-A73", { ARCH_V8, profile_CortexA } },
48 { "Cortex-A72", { ARCH_V8, profile_CortexA } },
49 { "Cortex-A65", { ARCH_V8r3, profile_CortexA } },
50 { "Cortex-A57", { ARCH_V8, profile_CortexA } },
51 { "Cortex-A55", { ARCH_V8r3, profile_CortexA } },
52 { "Cortex-A53", { ARCH_V8, profile_CortexA } },
53 { "Cortex-A35", { ARCH_V8, profile_CortexA } },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dnxp,lpc1850-rgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nxp,lpc1850-rgu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
14 const: nxp,lpc1850-rgu
22 clock-names:
24 - const: delay
25 - const: reg
27 '#reset-cells':
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H A Dnxp,lpc1850-rgu.txt8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
56 56 ARM Cortex-M0 application core (LPC4370 only)
59 60 ADCHS (12-bit ADC) (LPC4370 only)
65 rgu: reset-controller@40053000 {
66 compatible = "nxp,lpc1850-rgu";
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/freebsd/contrib/bearssl/src/
H A Dconfig.h29 * This file contains compile-time flags that can override the
32 * non-zero integer (normally 1). If the macro is not defined, then
37 * When BR_64 is enabled, 64-bit integer types are assumed to be
38 * efficient (i.e. the architecture has 64-bit registers and can
39 * do 64-bit operations as fast as 32-bit operations).
45 * When BR_LOMUL is enabled, then multiplications of 32-bit values whose
47 * substantially more efficient than 32-bit multiplications that yield
48 * 64-bit results. This is typically the case on low-end ARM Cortex M
49 * systems (M0, M0+, M1, and arguably M3 and M4 as well).
64 * When BR_SLOW_MUL15 is enabled, short multplications (on 15-bit words)
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
57 On 32-bit ARM v7 or later systems this property is required and matches
64 On ARM v8 64-bit systems this property is required and matches the
67 * If cpus node's #address-cells property is set to 2
75 * If cpus node's #address-cells property is set to 1
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H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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/freebsd/contrib/bearssl/samples/
H A Dcustom_profile.c41 * respectively. Of course, in a typical size-constrained application,
108 br_ssl_engine_set_versions(&cc->eng, BR_TLS10, BR_TLS12); in example_client_profile()
114 * -- cipher suites with a name ending in "SHA384" need "prf_sha384"; in example_client_profile()
115 * -- all others need "prf_sha256". in example_client_profile()
118 * use SHA-1 for the per-record MAC (that's what the final "SHA" in example_client_profile()
119 * means), but still SHA-256 for the PRF when selected along with in example_client_profile()
120 * the TLS-1.2 protocol version. in example_client_profile()
122 br_ssl_engine_set_prf10(&cc->eng, &br_tls10_prf); in example_client_profile()
123 br_ssl_engine_set_prf_sha256(&cc->eng, &br_tls12_sha256_prf); in example_client_profile()
124 br_ssl_engine_set_prf_sha384(&cc->eng, &br_tls12_sha384_prf); in example_client_profile()
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/freebsd/crypto/openssl/crypto/bn/asm/
H A Darmv4-mont.pl2 # Copyright 2007-2023 The OpenSSL Project Authors. All Rights Reserved.
22 # and compilers. The code was observed to provide +65-35% improvement
24 # +115-80% on Intel IXP425. This is compared to pre-bn_mul_mont code
25 # base and compiler generated code with in-lined umull and even umlal
36 # performance improvement on Cortex-A8 is ~45-100% depending on key
37 # length, more for longer keys. On Cortex-A15 the span is ~10-105%.
40 # rather because original integer-only code seems to perform
41 # suboptimally on S4. Situation on Cortex-A9 is unfortunately
44 # of percent worse than for integer-only code. The code is chosen
45 # for execution on all NEON-capable processors, because gain on
[all …]
H A Darmv8-mont.pl2 # Copyright 2015-2025 The OpenSSL Project Authors. All Rights Reserved.
20 # work. While it does improve RSA sign performance by 20-30% (less for
22 # faster and RSA4096 goes 15-20% slower on Cortex-A57. Multiplication
28 # compiler-generated code. Recall that compiler is instructed to use
36 # RSA/DSA performance by 25-40-60% depending on processor and key
38 # comparison to compiler-generated code. On Cortex-A57 improvement
40 # 50-70% improvement for RSA4096 sign. RSA2048 sign is ~25% faster
41 # on Cortex-A57 and ~60-100% faster on others.
49 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
50 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3308.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
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H A Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMProcessors.td4 //===----------------------------------------------------------------------===//
9 "Cortex-A5 ARM processors", []>;
11 "Cortex-A7 ARM processors", []>;
13 "Cortex-A8 ARM processors", []>;
15 "Cortex-A9 ARM processors", []>;
17 "Cortex-A12 ARM processors", []>;
19 "Cortex-A15 ARM processors", []>;
21 "Cortex-A17 ARM processors", []>;
23 "Cortex-A32 ARM processors", []>;
25 "Cortex-A35 ARM processors", []>;
[all …]
/freebsd/contrib/llvm-project/lldb/source/Utility/
H A DArchSpec.cpp1 //===-- ArchSpec.cpp ------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 #include "lldb/lldb-defines.h"
193 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
234 ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
236 ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
279 //===----------------------------------------------------------------------===//
286 // clang-format off
348 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
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/freebsd/crypto/libecc/include/libecc/words/
H A Dwords.h2 * Copyright (C) 2017 - This file is part of libecc project
7 * Jean-Pierre FLORI <jean-pierre.flori@ssi.gouv.fr>
25 * By default, 64-bit word size is used since it is the most reasonable
44 * we use WORDSIZE=64. This is obviously the case on 64-bit platforms,
45 * but this should also be the case on most 32-bit platforms where
46 * native instructions allow a 32-bit x 32-bit to 64-bit multiplication.
49 * Cortex-M0/M0+ for example does not have such a native multiplication
51 * This is also the case for old Thumb ARM CPUs (pre Thumb-2).
53 * On 8-bit and 16-bit platform, we prefer to let the user decide on the best
75 * higher than (WORD_BITS - 1). These macros emulate
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/freebsd/contrib/bearssl/src/symcipher/
H A Dpoly1305_ctmul32.c34 * Implementation notes: we split the 130-bit values into ten in poly1305_inner()
35 * 13-bit words. This gives us some space for carries and allows in poly1305_inner()
36 * using only 32x32->32 multiplications, which are way faster than in poly1305_inner()
37 * 32x32->64 multiplications on the ARM Cortex-M0/M0+, and also in poly1305_inner()
38 * help in making constant-time code on the Cortex-M3. in poly1305_inner()
40 * Since we compute modulo 2^130-5, the "upper words" become in poly1305_inner()
45 * In each loop iteration, a[] and r[] words are 13-bit each, in poly1305_inner()
58 * If there is a partial block, right-pad it with zeros. in poly1305_inner()
108 * a 32-bit word and still have some room for carries. in poly1305_inner()
116 * (they are 5 times a 13-bit word) so the full summation in poly1305_inner()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
28 ARM_FPU("vfpv3-fp16", FK_VFPV3_FP16, FPUVersion::VFPV3_FP16,
30 ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FPUVersion::VFPV3, NeonSupportLevel::None,
32 ARM_FPU("vfpv3-d16-fp16", FK_VFPV3_D16_FP16, FPUVersion::VFPV3_FP16,
36 ARM_FPU("vfpv3xd-fp16", FK_VFPV3XD_FP16, FPUVersion::VFPV3_FP16,
40 ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FPUVersion::VFPV4, NeonSupportLevel::None,
42 ARM_FPU("fpv4-sp-d16", FK_FPV4_SP_D16, FPUVersion::VFPV4,
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/freebsd/crypto/libecc/
H A DREADME.md11 Copyright (C) 2017-2023
20 * Jean-Pierre FLORI (<mailto:jpflori@gmail.com>)
30 in the [ISO 14888-3:2018](https://www.iso.org/standard/76382.html)
34 * Core ISO 14888-3:2018 algorithms: ECDSA, ECKCDSA, ECGDSA, ECRDSA, EC{,O}SDSA, ECFSDSA, SM2.
36 …* BIGN (as standardized in [STB 34.101.45-2013](https://github.com/bcrypto/bign)). We allow a more…
38 … "Schnorr" Bitcoin proposal, as specified in [bip-0340](https://github.com/bitcoin/bips/blob/maste…
39 …tandard as we allow any curve and any hash function (the standard mandates SECP256K1 with SHA-256).
42 …-CDH (Elliptic Curve Cryptography Cofactor Diffie-Hellman) as described in [section 5.7.1.2 of the…
45 …STR3410-2001-CryptoPro{A,B,C,XchA,XchB,Test}-ParamSet, GOSTR3410-2012-{256,512}-ParamSet{A,B,C}, G…
47 * **Hash functions**: SHA-2 and SHA-3 hash functions (224, 256, 384, 512), SM3, RIPEMD-160,
[all …]
/freebsd/contrib/bearssl/
H A DREADME.txt3 The most up-to-date documentation is supposed to be available on the
8 BearSSL is considered beta-level software. Most planned functionalities
13 utterly crazy move. BearSSL is free, open-source software, provided
22 - You can use and reuse the library as you wish, and modify it, and
26 - The only obligation that the license terms put upon you is that you
37 command-line tools. There is no installer yet. The library _can_ be
50 configuration file (that targets cross-compilation for an Atmel board
51 that features a Cortex-M0+ CPU), type:
59 Some compile-time options can be set through macros, either on the
60 compiler command-line, or in the `src/config.h` file. See the comments
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/freebsd/contrib/bearssl/src/hash/
H A Dghash_ctmul32.c28 * This implementation uses 32-bit multiplications, and only the low
30 * the ARM Cortex M0 and M0+, whose multiplication opcode does not yield
37 * The implementation trick that is used here is bit-reversing (bit 0
41 * In other words, if we bit-reverse (over 32 bits) the operands, then we
42 * bit-reverse (over 64 bits) the result.
75 * Bit-reverse a 32-bit word.
102 * eighteen 32-bit multiplications instead of nine. in br_ghash_ctmul32()
136 len -= 16; in br_ghash_ctmul32()
139 memset(tmp + len, 0, (sizeof tmp) - len); in br_ghash_ctmul32()
151 * 32x32 multiplications. With the bit-reversal trick, in br_ghash_ctmul32()
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H A Dghash_ctmul.c31 * bits per 32-bit word, spaced every fourth bit. Accumulated carries
34 * It would be possible to use a 3-bit spacing, allowing two operands,
35 * one with 7 non-zero data bits, the other one with 10 or 11 non-zero
43 * not. A typical example is the ARM Cortex M0+, which exists in two
44 * versions: one with a 1-cycle multiplication opcode, the other with
45 * a 32-cycle multiplication opcode. They both use exactly the same
47 * at compile-time.
56 * This implementation uses Karatsuba-like reduction to make fewer
61 * reversed on low-end platforms with expensive multiplications.
88 * (x0+W*x1)*(y0+W*y1) -> a0:b0 in bmul()
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/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp1 //===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
18 #include "llvm/Config/llvm-config.h"
25 // Include the platform-specific parts of this class.
54 #define DEBUG_TYPE "host-detection"
56 //===----------------------------------------------------------------------===//
60 //===----------------------------------------------------------------------===//
78 // and so we must use an operating-system interface to determine the current in getHostCPUNameForPowerPC()
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/freebsd/contrib/bearssl/inc/
H A Dbearssl_rsa.h50 * such integers are represented with big-endian unsigned notation:
55 * relevant bytes. As a general rule, minimal-length encoding is not
60 * - the modulus (`n`);
61 * - the public exponent (`e`).
66 * - the modulus (`n`);
67 * - the public exponent (`e`);
68 * - the private exponent (`d`);
69 * - the first prime factor (`p`);
70 * - the second prime factor (`q`);
71 * - the first reduced exponent (`dp`, which is `d` modulo `p-1`);
[all …]
/freebsd/contrib/llvm-project/lldb/include/lldb/Utility/
H A DArchSpec.h1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 #include "lldb/lldb-enumerations.h"
14 #include "lldb/lldb-forward.h"
15 #include "lldb/lldb-private-enumerations.h"
56 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE
77 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float
78 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float
80 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64
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