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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,realview.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
31 - const: arm,realview-pb1176
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H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMProcessors.td4 //===----------------------------------------------------------------------===//
9 "Cortex-A5 ARM processors", []>;
11 "Cortex-A7 ARM processors", []>;
12 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
13 "Cortex-A8 ARM processors", []>;
15 "Cortex-A9 ARM processors", []>;
17 "Cortex-A12 ARM processors", []>;
19 "Cortex-A15 ARM processors", []>;
21 "Cortex-A17 ARM processors", []>;
23 "Cortex-A32 ARM processors", []>;
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-pba8.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
27 model = "ARM RealView Platform Baseboard for Cortex-A8";
28 compatible = "arm,realview-pba8";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "arm,realview-smp";
38 compatible = "arm,cortex-a8";
44 compatible = "arm,cortex-a8-pmu";
45 interrupt-parent = <&intc>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DARMBuildAttributes.h1 //===-- ARMBuildAttributes.h - ARM Build Attributes -------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // ELF for the ARM Architecture r2.09 - November 30, 2012
16 //===----------------------------------------------------------------------===//
103 v7 = 10, // e.g. Cortex A8, Cortex M3
104 v6_M = 11, // e.g. Cortex M1
108 v8_R = 15, // e.g. Cortex R52
116 Not_Applicable = 0, // pre v7, or cross-profile code
117 ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8)
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/freebsd/contrib/opencsd/decoder/source/
H A Dtrc_core_arch_map.cpp44 { "Cortex-A77", { ARCH_V8r3, profile_CortexA } },
45 { "Cortex-A76", { ARCH_V8r3, profile_CortexA } },
46 { "Cortex-A75", { ARCH_V8r3, profile_CortexA } },
47 { "Cortex-A73", { ARCH_V8, profile_CortexA } },
48 { "Cortex-A72", { ARCH_V8, profile_CortexA } },
49 { "Cortex-A65", { ARCH_V8r3, profile_CortexA } },
50 { "Cortex-A57", { ARCH_V8, profile_CortexA } },
51 { "Cortex-A55", { ARCH_V8r3, profile_CortexA } },
52 { "Cortex-A53", { ARCH_V8, profile_CortexA } },
53 { "Cortex-A35", { ARCH_V8, profile_CortexA } },
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/freebsd/sys/arm/arm/
H A Dpmu_fdt.c1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
45 {"arm,armv8-pmuv3", 1},
46 {"arm,cortex-a77-pmu", 1},
47 {"arm,cortex-a76-pmu", 1},
48 {"arm,cortex-a75-pmu", 1},
49 {"arm,cortex-a73-pmu", 1},
50 {"arm,cortex-a72-pmu", 1},
51 {"arm,cortex-a65-pmu", 1},
52 {"arm,cortex-a57-pmu", 1},
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H A Dcpufunc_asm_armv7.S1 /*-
36 .cpu cortex-a8
H A Didentcpu-v6.c3 /*-
76 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5",
78 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7",
80 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8",
82 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9",
84 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12",
86 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15",
88 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17",
90 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53",
92 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57",
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/freebsd/tools/tools/nanobsd/embedded/
H A Dbeaglebone.cfg2 #-
4 # Copyright (c) 2010-2011 iXsystems, Inc.
32 NANO_BOOT_PKG=u-boot-beaglebone
33 NANO_CPUTYPE=cortex-a8
/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghash-armv4.pl2 # Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # The module implements "4-bit" GCM GHASH function and underlying
20 # single multiplication operation in GF(2^128). "4-bit" means that it
21 # uses 256 bytes per-key table [+32 bytes shared table]. There is no
24 # 32 instructions long and on single-issue core should execute in <40
27 # compiler-generated one...
31 # Rescheduling for dual-issue pipeline resulted in 8.5% improvement on
32 # Cortex A8 core and ~25 cycles per processed byte (which was observed
33 # to be ~3 times faster than gcc-generated code:-)
37 # Profiler-assisted and platform-specific optimization resulted in 7%
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/freebsd/sys/arm/ti/
H A Dti_smc.S1 /*-
28 .cpu cortex-a8
34 stmfd sp!, {r4-r12, lr}
38 ldmfd sp!, {r4-r12, pc}
/freebsd/share/examples/etc/
H A Dmake.conf25 # generated code. This controls processor-specific optimizations in
33 # bdver1, btver2, btver1, amdfam10, opteron-sse3,
34 # athlon64-sse3, k8-sse3, opteron, athlon64, athlon-fx,
35 # k8, athlon-mp, athlon-xp, athlon-4, athlon-tbird,
36 # athlon, k7, geode, k6-3, k6-2, k6
38 # cascadelake, tremont, goldmont-plus, icelake-server,
39 # icelake-client, cannonlake, knm, skylake-avx512, knl,
43 # pentium3m, pentium3, pentium-m, pentium2, pentiumpro,
44 # pentium-mmx, pentium, i486
45 # (VIA CPUs) c7, c3-2, c3
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/freebsd/contrib/llvm-project/lld/ELF/
H A DARMErrataFix.cpp1 //===- ARMErrataFix.cpp ---------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Cortex-a8 erratum 657417 "A 32bit branch instruction that spans 2 4K regions
12 // Cortex-A8. A high level description of the patching technique is given in
14 //===----------------------------------------------------------------------===//
40 // 32-bit B.w instruction encoded as a pair of halfwords 0xf7fe 0xbfff
49 // - There is a 32-bit Thumb-2 branch instruction with an address of the form
52 // - The branch instruction is one of BLX, BL, B.w BCC.w
53 // - The instruction preceding the branch is a 32-bit non-branch instruction.
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/freebsd/lib/libpmc/
H A Dpmc.31 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
40 The library is implemented using the lower-level facilities offered by
50 .Bl -bullet
53 These PMCs measure events in a whole-system manner, i.e., independent
57 Non-privileged process are allowed to allocate system scope PMCs if the
61 is non-zero.
72 .Bl -bullet
90 The library uses human-readable strings to name the event being
99 Additionally, process-scope PMCs have to be attached to one or more
101 A process-scope PMC may be attached to those target processes
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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha1-armv4-large.pl2 # Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
21 # Size/performance trade-off
26 # armv4-small 392/+29% 1958/+64% 2250/+96%
27 # armv4-compact 740/+89% 1552/+26% 1840/+22%
28 # armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
40 # i-cache availability, branch penalties, etc.
47 # [***] which is also ~35% better than compiler generated code. Dual-
48 # issue Cortex A8 core was measured to process input block in
53 # Rescheduling for dual-issue pipeline resulted in 13% improvement on
54 # Cortex A8 core and in absolute terms ~870 cycles per input block
[all …]
H A Dsha512-armv4.pl2 # Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
22 # by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
27 # Rescheduling for dual-issue pipeline resulted in 6% improvement on
28 # Cortex A8 core and ~40 cycles per processed byte.
32 # Profiler-assisted and platform-specific optimization resulted in 7%
33 # improvement on Coxtex A8 core and ~38 cycles per byte.
37 # Add NEON implementation. On Cortex A8 it was measured to process
38 # one byte in 23.3 cycles or ~60% faster than integer-only code.
44 # Technical writers asserted that 3-way S4 pipeline can sustain
46 # not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
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/freebsd/contrib/bearssl/src/hash/
H A Dghash_ctmul.c31 * bits per 32-bit word, spaced every fourth bit. Accumulated carries
34 * It would be possible to use a 3-bit spacing, allowing two operands,
35 * one with 7 non-zero data bits, the other one with 10 or 11 non-zero
43 * not. A typical example is the ARM Cortex M0+, which exists in two
44 * versions: one with a 1-cycle multiplication opcode, the other with
45 * a 32-cycle multiplication opcode. They both use exactly the same
47 * at compile-time.
56 * This implementation uses Karatsuba-like reduction to make fewer
61 * reversed on low-end platforms with expensive multiplications.
75 uint32_t a0, a1, a2, a3, a4, a5, a6, a7, a8; in bmul() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
28 ARM_FPU("vfpv3-fp16", FK_VFPV3_FP16, FPUVersion::VFPV3_FP16,
30 ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FPUVersion::VFPV3, NeonSupportLevel::None,
32 ARM_FPU("vfpv3-d16-fp16", FK_VFPV3_D16_FP16, FPUVersion::VFPV3_FP16,
36 ARM_FPU("vfpv3xd-fp16", FK_VFPV3XD_FP16, FPUVersion::VFPV3_FP16,
40 ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FPUVersion::VFPV4, NeonSupportLevel::None,
42 ARM_FPU("fpv4-sp-d16", FK_FPV4_SP_D16, FPUVersion::VFPV4,
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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dti-cpufreq.txt6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
8 used to determine which OPPs from the operating-points-v2 table get enabled
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,
20 - syscon: A phandle pointing to a syscon node representing the control module
24 --------------------
25 - "vdd-supply", "vbb-supply": to define two regulators for dra7xx
[all …]
/freebsd/sys/contrib/device-tree/src/arm/cnxt/
H A Dcx92755.dtsi8 * This file is dual-licensed: you can use it either under the terms
48 #address-cells = <1>;
49 #size-cells = <1>;
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a8";
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <200000000>;
[all …]
/freebsd/share/mk/
H A Dbsd.cpu.mk34 CPUTYPE = skylake-avx512
35 . elif ${CPUTYPE} == "core-avx2"
37 . elif ${CPUTYPE} == "core-avx-i"
39 . elif ${CPUTYPE} == "corei7-avx"
65 . elif ${CPUTYPE} == "p-m"
66 CPUTYPE = pentium-m
72 CPUTYPE = pentium-mmx
83 # http://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
84 # http://gcc.gnu.org/onlinedocs/gcc/RS-6000-and-PowerPC-Options.html
85 # http://gcc.gnu.org/onlinedocs/gcc/SPARC-Options.html
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParser.cpp1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
165 // We have to specify the + and - versions of the name in full so in getFPUFeatures()
172 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16}, in getFPUFeatures()
173 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16}, in getFPUFeatures()
174 {"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None}, in getFPUFeatures()
175 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16}, in getFPUFeatures()
176 {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16}, in getFPUFeatures()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Processors.td1 //=- AArch64Processors.td - Describe AArch64 Processors ------*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 "Cortex-A35 ARM processors">;
21 "Cortex-A53 ARM processors", [
28 "Cortex-A55 ARM processors", [
35 "Cortex-A510 ARM processors", [
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