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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PM
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H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a numbe
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H A Dscu.txt3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
4 with a Snoop Control Unit. The register range is usually 256 (0x100)
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
16 - compatible : Should be:
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
19 "arm,arm11mp-scu"
21 - reg : Specify the base address and the size of the SCU register window.
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H A Darm,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
14 with a Snoop Control Unit. The register range is usually 256 (0x100)
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
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H A Darm,corstone1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vishnu Banavath <vishnu.banavath@arm.com>
11 - Rui Miguel Silva <rui.silva@linaro.org>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
21 a secure SoC for a range of rich IoT applications, for example gateways, smart
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H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
22 enter/exit specific idle states on a given processor.
27 - Running
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H A Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-jun
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H A Darm,realview.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
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/freebsd/contrib/opencsd/decoder/source/
H A Dtrc_core_arch_map.cpp25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
44 { "Cortex-A77", { ARCH_V8r3, profile_CortexA } },
45 { "Cortex-A76", { ARCH_V8r3, profile_CortexA } },
46 { "Cortex-A75", { ARCH_V8r3, profile_CortexA } },
47 { "Cortex-A73", { ARCH_V8, profile_CortexA } },
48 { "Cortex-A72", { ARCH_V8, profile_CortexA } },
49 { "Cortex-A65", { ARCH_V8r3, profile_CortexA } },
50 { "Cortex-A57", { ARCH_V8, profile_CortexA } },
51 { "Cortex-A55", { ARCH_V8r3, profile_CortexA } },
52 { "Cortex-A53", { ARCH_V8, profile_CortexA } },
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
28 ARM_FPU("vfpv3-fp16", FK_VFPV3_FP16, FPUVersion::VFPV3_FP16,
30 ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FPUVersion::VFPV3, NeonSupportLevel::None,
32 ARM_FPU("vfpv3-d16-fp16", FK_VFPV3_D16_FP16, FPUVersion::VFPV3_FP16,
36 ARM_FPU("vfpv3xd-fp16", FK_VFPV3XD_FP16, FPUVersion::VFPV3_FP16,
40 ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FPUVersion::VFPV4, NeonSupportLevel::None,
42 ARM_FPU("fpv4-sp-d16", FK_FPV4_SP_D16, FPUVersion::VFPV4,
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/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-topology.txt6 1 - Introduction
9 In a SMP system, the hierarchy of CPUs is defined through three entities that
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
35 A topology description containing phandles to cpu nodes that are not compliant
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H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-state
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H A Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Processors.td1 //=- AArch64Processors.td - Describe AArch64 Processors ------*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 "Cortex-A35 ARM processors">;
21 "Cortex-A53 ARM processors", [
28 "Cortex-A55 ARM processors", [
35 "Cortex-A510 ARM processors", [
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Darm,twd.txt3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
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H A Darm,twd-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
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/freebsd/sys/arm/arm/
H A Dpmu_fdt.c1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 {"arm,armv8-pmuv3", 1},
46 {"arm,cortex-a77-pmu", 1},
47 {"arm,cortex-a76-pmu", 1},
48 {"arm,cortex-a75-pmu", 1},
49 {"arm,cortex-a73-pmu", 1},
50 {"arm,cortex-a72-pmu", 1},
51 {"arm,cortex-a65-pmu", 1},
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
13 ARM SMP cores are often associated with a GIC, providing per processor
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-eb-a9mp.dts4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
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H A Darm-realview-pbx-a9.dts4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
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/freebsd/share/examples/etc/
H A Dmake.conf25 # generated code. This controls processor-specific optimizations in
33 # bdver1, btver2, btver1, amdfam10, opteron-sse3,
34 # athlon64-sse3, k8-sse3, opteron, athlon64, athlon-fx,
35 # k8, athlon-mp, athlon-xp, athlon-4, athlon-tbird,
36 # athlon, k7, geode, k6-3, k6-2, k6
38 # cascadelake, tremont, goldmont-plus, icelake-server,
39 # icelake-client, cannonlake, knm, skylake-avx512, knl,
43 # pentium3m, pentium3, pentium-m, pentium2, pentiumpro,
44 # pentium-mmx, pentium, i486
45 # (VIA CPUs) c7, c3-2, c3
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/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Darm,twd-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp1 //===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
18 #include "llvm/Config/llvm-config.h"
25 // Include the platform-specific parts of this class.
54 #define DEBUG_TYPE "host-detection"
56 //===----------------------------------------------------------------------===//
60 //===----------------------------------------------------------------------===//
78 // and so we must use an operating-system interface to determine the current in getHostCPUNameForPowerPC()
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/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp.txt2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
8 uses CPU as a device.
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
30 operating-points = <
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