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/linux/Documentation/trace/coresight/
H A Dcoresight-ect.rst4 CoreSight Embedded Cross Trigger (CTI & CTM).
15 devices and interconnects them via the Cross Trigger Matrix (CTM) to other
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
33 become active. The active channel is propagated to other CTIs via the CTM,
53 All the CTI devices are associated with a CTM. On many systems there will be a
54 single effective CTM (one CTM, or multiple CTMs all interconnected), but it is
55 possible that systems can have nets of CTIs+CTM that are not interconnected by
56 a CTM to each other. On these systems a CTM index is declared to associate
57 CTI devices that are interconnected via a given CTM.
82 * ``ctmid`` : associated CTM - only relevant if system has multiple CTI+CTM
[all …]
H A Dcoresight-config.rst19 the cross trigger components such as CTI and CTM. These system settings can
/linux/drivers/gpu/drm/vc4/
H A Dvc4_kms.c30 struct drm_color_ctm *ctm; member
139 struct drm_color_ctm *ctm = ctm_state->ctm; in vc4_ctm_commit() local
145 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
147 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
149 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
152 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
154 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
156 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
159 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
161 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
[all …]
/linux/drivers/gpu/drm/omapdrm/
H A Domap_crtc.c381 static void omap_crtc_cpr_coefs_from_ctm(const struct drm_color_ctm *ctm, in omap_crtc_cpr_coefs_from_ctm() argument
384 cpr->rr = omap_crtc_s31_32_to_s2_8(ctm->matrix[0]); in omap_crtc_cpr_coefs_from_ctm()
385 cpr->rg = omap_crtc_s31_32_to_s2_8(ctm->matrix[1]); in omap_crtc_cpr_coefs_from_ctm()
386 cpr->rb = omap_crtc_s31_32_to_s2_8(ctm->matrix[2]); in omap_crtc_cpr_coefs_from_ctm()
387 cpr->gr = omap_crtc_s31_32_to_s2_8(ctm->matrix[3]); in omap_crtc_cpr_coefs_from_ctm()
388 cpr->gg = omap_crtc_s31_32_to_s2_8(ctm->matrix[4]); in omap_crtc_cpr_coefs_from_ctm()
389 cpr->gb = omap_crtc_s31_32_to_s2_8(ctm->matrix[5]); in omap_crtc_cpr_coefs_from_ctm()
390 cpr->br = omap_crtc_s31_32_to_s2_8(ctm->matrix[6]); in omap_crtc_cpr_coefs_from_ctm()
391 cpr->bg = omap_crtc_s31_32_to_s2_8(ctm->matrix[7]); in omap_crtc_cpr_coefs_from_ctm()
392 cpr->bb = omap_crtc_s31_32_to_s2_8(ctm->matrix[8]); in omap_crtc_cpr_coefs_from_ctm()
[all …]
/linux/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c199 * Check if there is a new CTM and if it contains valid input. Valid here means
209 struct drm_color_ctm *ctm; in malidp_crtc_atomic_check_ctm() local
215 if (!state->ctm) in malidp_crtc_atomic_check_ctm()
218 if (crtc->state->ctm && (crtc->state->ctm->base.id == in malidp_crtc_atomic_check_ctm()
219 state->ctm->base.id)) in malidp_crtc_atomic_check_ctm()
223 * The size of the ctm is checked in in malidp_crtc_atomic_check_ctm()
226 ctm = (struct drm_color_ctm *)state->ctm->data; in malidp_crtc_atomic_check_ctm()
227 for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) { in malidp_crtc_atomic_check_ctm()
229 s64 val = ctm->matrix[i]; in malidp_crtc_atomic_check_ctm()
H A Dmalidp_drv.c100 if (!crtc->state->ctm) { in malidp_atomic_commit_update_coloradj()
107 if (!old_state->ctm || (crtc->state->ctm->base.id != in malidp_atomic_commit_update_coloradj()
108 old_state->ctm->base.id)) in malidp_atomic_commit_update_coloradj()
/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti.h101 * @ctm_id: which CTM this device is connected to (by default it is
102 * assumed there is a single CTM per SoC, ID 0).
121 * @nr_ctm_channels: number of available CTM channels - from ID register.
136 * @ctigate: gate channel output from CTI to CTM.
169 * @ctidev: Extra information needed by the CTI/CTM framework.
H A Dcoresight-cti-platform.c34 #define CTI_DT_CTM_ID "arm,cti-ctm-id"
439 /* get any CTM ID - defaults to 0 */ in cti_plat_get_hw_data()
H A Dcoresight-cti-core.c33 * the same CTM, in general this is the case but does not always have to be.
36 /* net of CTI devices connected via CTM */
214 /* DEVID[19:16] - number of CTM channels */
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_ccorr.c107 struct drm_property_blob *blob = state->ctm; in mtk_ccorr_ctm_set()
108 struct drm_color_ctm *ctm; in mtk_ccorr_ctm_set() local
118 ctm = (struct drm_color_ctm *)blob->data; in mtk_ccorr_ctm_set()
119 input = ctm->matrix; in mtk_ccorr_ctm_set()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_crtc.c793 struct drm_color_ctm *ctm; in _dpu_crtc_get_pcc_coeff() local
797 ctm = (struct drm_color_ctm *)state->ctm->data; in _dpu_crtc_get_pcc_coeff()
799 if (!ctm) in _dpu_crtc_get_pcc_coeff()
802 cfg->r.r = CONVERT_S3_15(ctm->matrix[0]); in _dpu_crtc_get_pcc_coeff()
803 cfg->g.r = CONVERT_S3_15(ctm->matrix[1]); in _dpu_crtc_get_pcc_coeff()
804 cfg->b.r = CONVERT_S3_15(ctm->matrix[2]); in _dpu_crtc_get_pcc_coeff()
806 cfg->r.g = CONVERT_S3_15(ctm->matrix[3]); in _dpu_crtc_get_pcc_coeff()
807 cfg->g.g = CONVERT_S3_15(ctm->matrix[4]); in _dpu_crtc_get_pcc_coeff()
808 cfg->b.g = CONVERT_S3_15(ctm->matrix[5]); in _dpu_crtc_get_pcc_coeff()
810 cfg->r.b = CONVERT_S3_15(ctm->matrix[6]); in _dpu_crtc_get_pcc_coeff()
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dbase907c.c138 const struct drm_color_ctm *ctm) in base907c_csc() argument
150 *val = csc_drm_to_base(ctm->matrix[j * 3 + i]); in base907c_csc()
H A Dwndw.c427 if (wndw->func->csc && asyh->state.ctm) { in nv50_wndw_atomic_check_lut()
428 const struct drm_color_ctm *ctm = asyh->state.ctm->data; in nv50_wndw_atomic_check_lut() local
429 wndw->func->csc(wndw, asyw, ctm); in nv50_wndw_atomic_check_lut()
/linux/Documentation/gpu/amdgpu/display/
H A Ddisplay-manager.rst58 color transformation matrix (CTM) and gamma, and two properties for degamma and
63 CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is
H A Ddcn2_cm_drm_current.svg790 style="font-size:18.6667px">CTM</tspan></text>
H A Ddcn3_cm_drm_current.svg851 style="font-size:18.6667px">CTM</tspan></text>
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.h902 * @ctm:
907 struct drm_property_blob *ctm; member
/linux/Documentation/networking/device_drivers/ethernet/netronome/
H A Dnfp.rst341 * A CTM buffer could not be allocated.
/linux/Documentation/gpu/
H A Dkomeda-kms.rst357 Like set mode, gamma, ctm for KMS all target on CRTC-obj, but komeda needs
/linux/sound/isa/sb/
H A Dsb16.c145 /* Sound Blaster Vibra16CL - added by ctm@ardi.com */
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_target.c641 * to local-island CTM with a 32-but address (high-locality in nfp_encode_mu()
/linux/include/drm/
H A Ddrm_mode_config.h808 * convert the colors, after the CTM matrix, to the gamma space of the
/linux/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_component.c1072 if (crtc_st->ctm) { in d71_improc_update()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h184 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
/linux/drivers/tty/
H A Dtty_io.c39 * -- ctm@ardi.com, 9Sep95

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