| /linux/tools/testing/selftests/kvm/x86/ |
| H A D | ucna_injection_test.c | 79 u64 ctl2; in ucna_injection_guest_code() local
85 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in ucna_injection_guest_code()
86 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); in ucna_injection_guest_code()
97 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in ucna_injection_guest_code()
98 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN); in ucna_injection_guest_code()
109 u64 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in cmci_disabled_guest_code() local
110 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); in cmci_disabled_guest_code()
117 u64 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in cmci_enabled_guest_code() local
118 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT); in cmci_enabled_guest_code()
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| /linux/drivers/rtc/ |
| H A D | rtc-rs5c348.c | 79 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
81 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
124 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
126 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
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| H A D | rtc-rzn1.c | 317 u32 subu = 0, ctl2; in rzn1_rtc_set_offset() local
351 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2, in rzn1_rtc_set_offset()
352 !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000); in rzn1_rtc_set_offset()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | dvo_tfp410.c | 209 u8 ctl2; in tfp410_detect() local
211 if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) { in tfp410_detect()
212 if (ctl2 & TFP410_CTL_2_RSEN) in tfp410_detect()
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| H A D | intel_backlight_regs.h | 79 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
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| H A D | intel_ddi.c | 635 u32 ctl2 = 0; in intel_ddi_enable_transcoder_func() local
641 ctl2 |= PORT_SYNC_MODE_ENABLE | in intel_ddi_enable_transcoder_func()
647 ctl2); in intel_ddi_enable_transcoder_func()
3939 u32 ctl2 = intel_de_read(display, in bdw_transcoder_master_readout() local
3942 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) in bdw_transcoder_master_readout()
3945 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); in bdw_transcoder_master_readout()
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| /linux/drivers/video/fbdev/ |
| H A D | arcfb.c | 394 unsigned char ctl2; in arcfb_ioctl() local
396 ctl2 = ks108_readb_ctl2(info->par); in arcfb_ioctl()
397 if (copy_to_user(argp, &ctl2, sizeof(ctl2))) in arcfb_ioctl()
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| /linux/sound/soc/codecs/ |
| H A D | cs35l33.h | 25 #define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */
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| H A D | cs35l35.h | 28 #define CS35L35_SP_FMT_CTL2 0x0E /* Serial Port Format CTL2 */
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| /linux/tools/testing/selftests/vfio/lib/drivers/nv_falcon/ |
| H A D | hw.h | 168 /* FBIF CTL2 offset (relative to fbif_ctl) */
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| /linux/sound/mips/ |
| H A D | hal2.h | 141 /* Bits in CTL2 register */
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| /linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | rvu_cpt.c | 957 u64 ctl, ctl2; in rvu_mbox_handler_cpt_lf_reset() local
970 ctl2 = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf)); in rvu_mbox_handler_cpt_lf_reset()
978 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), ctl2); in rvu_mbox_handler_cpt_lf_reset()
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| H A D | rvu_debugfs.c | 3910 seq_printf(filp, "CPT Lf[%u] CTL2 0x%llx\n", lf, reg); in rvu_dbg_cpt_lfs_info_display()
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| /linux/drivers/gpu/drm/loongson/ |
| H A D | lsdc_regs.h | 323 * data island. The values of CTL0, CTL1, CTL2, and CTL3 indicate the type of
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| /linux/drivers/net/wireless/ath/ath9k/ |
| H A D | eeprom_4k.c | 124 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2); in ath9k_dump_4k_modal_eeprom()
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| /linux/drivers/net/wireless/mediatek/mt76/ |
| H A D | mt76x02_mac.c | 395 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); in mt76x02_mac_write_txwi()
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