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Searched full:ctl2 (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/mtd/nand/raw/
H A Dcafe_nand.c66 uint32_t ctl2; member
174 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); in cafe_nand_cmdfunc()
176 cafe->ctl2 &= ~(1<<30); in cafe_nand_cmdfunc()
243 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); in cafe_nand_cmdfunc()
245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); in cafe_nand_cmdfunc()
248 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", in cafe_nand_cmdfunc()
298 WARN_ON(cafe->ctl2 & (1<<30)); in cafe_nand_cmdfunc()
310 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); in cafe_nand_cmdfunc()
314 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); in cafe_nand_cmdfunc()
544 cafe->ctl2 |= (1<<30); in cafe_nand_write_page_lowlevel()
[all …]
/linux/drivers/rtc/
H A Drtc-rs5c348.c79 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
81 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
124 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
126 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
H A Drtc-rzn1.c318 u32 subu = 0, ctl2; in rzn1_rtc_set_offset() local
352 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2, in rzn1_rtc_set_offset()
353 !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000); in rzn1_rtc_set_offset()
/linux/drivers/hwmon/
H A Dlm93.c291 * The two PWM CTL2 registers can read something other than what was
1752 u8 ctl2, ctl4; in pwm_show() local
1755 ctl2 = data->block9[nr][LM93_PWM_CTL2]; in pwm_show()
1757 if (ctl2 & 0x01) /* show user commanded value if enabled */ in pwm_show()
1760 rc = LM93_PWM_FROM_REG(ctl2 >> 4, (ctl4 & 0x07) ? in pwm_show()
1771 u8 ctl2, ctl4; in pwm_store() local
1780 ctl2 = lm93_read_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2)); in pwm_store()
1782 ctl2 = (ctl2 & 0x0f) | LM93_PWM_TO_REG(val, (ctl4 & 0x07) ? in pwm_store()
1785 data->pwm_override[nr] = LM93_PWM_FROM_REG(ctl2 >> 4, in pwm_store()
1788 lm93_write_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2), ctl2); in pwm_store()
[all …]
/linux/drivers/video/fbdev/
H A Darcfb.c394 unsigned char ctl2; in arcfb_ioctl() local
396 ctl2 = ks108_readb_ctl2(info->par); in arcfb_ioctl()
397 if (copy_to_user(argp, &ctl2, sizeof(ctl2))) in arcfb_ioctl()
/linux/drivers/pci/pcie/
H A Daspm.c643 u32 ctl1 = 0, ctl2 = 0; in aspm_calc_l12_info() local
660 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale1) | in aspm_calc_l12_info()
664 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale2) | in aspm_calc_l12_info()
692 ctl2 == pctl2 && ctl2 == cctl2) in aspm_calc_l12_info()
709 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
710 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_backlight_regs.h79 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_b0.c679 txd->ctl2 = 0; in hw_atl_b0_hw_ring_tx_xmit()
690 txd->ctl2 |= (buff->mss << 16); in hw_atl_b0_hw_ring_tx_xmit()
698 txd->ctl2 |= (buff->len_l4 << 8) | in hw_atl_b0_hw_ring_tx_xmit()
715 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14); in hw_atl_b0_hw_ring_tx_xmit()
719 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN; in hw_atl_b0_hw_ring_tx_xmit()
H A Dhw_atl_utils.h21 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */ member
/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml118 hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
/linux/sound/soc/codecs/
H A Dcs35l33.h25 #define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */
H A Dcs35l35.h28 #define CS35L35_SP_FMT_CTL2 0x0E /* Serial Port Format CTL2 */
/linux/sound/mips/
H A Dhal2.h141 /* Bits in CTL2 register */
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_cpt.c957 u64 ctl, ctl2; in rvu_mbox_handler_cpt_lf_reset() local
970 ctl2 = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf)); in rvu_mbox_handler_cpt_lf_reset()
978 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), ctl2); in rvu_mbox_handler_cpt_lf_reset()
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_regs.h323 * data island. The values of CTL0, CTL1, CTL2, and CTL3 indicate the type of
/linux/drivers/net/wireless/ath/ath9k/
H A Deeprom_4k.c124 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2); in ath9k_dump_4k_modal_eeprom()
/linux/drivers/spi/
H A Dspi-sprd.c82 /* Bits & mask definition for register CTL2 */
/linux/drivers/soc/tegra/
H A Dpmc.c3978 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
/linux/arch/x86/kvm/vmx/
H A Dtdx.c2127 /* MSR_IA32_MCx_{CTL, STATUS, ADDR, MISC, CTL2} */ in tdx_has_emulated_msr()