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/linux/arch/arm/include/asm/
H A Dcti.h41 * struct cti - cross trigger interface struct
42 * @base: mapped virtual address for the cti base
43 * @irq: irq number for the cti
47 * cti struct used to operate cti registers.
49 struct cti { struct
56 * cti_init - initialize the cti instance argument
57 * @cti: cti instance
58 * @base: mapped virtual address for the cti base
59 * @irq: irq number for the cti
64 * @base, @irq and @trig_out to cti.
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cti.yaml5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
17 The CTI component properties define the connections between the individual
18 CTI and the components it is directly connected to, consisting of input and
20 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
30 In general the connections between CTI and components via the trigger signals
31 are implementation defined, except when the CTI is connected to an ARM v8
35 between CTI and the CPU core and ETM if present. In the case of a v8
36 architecturally connected CTI an additional compatible string is used to
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-coresight.dtsi369 /* CTI 0 - TMC and TPIU connections */
370 cti@f6403000 {
371 compatible = "arm,coresight-cti", "arm,primecell";
378 /* CTI - CPU-0 */
379 cti@f6598000 {
380 compatible = "arm,coresight-cti-v8-arch",
381 "arm,coresight-cti", "arm,primecell";
391 /* CTI - CPU-1 */
392 cti@f6599000 {
393 compatible = "arm,coresight-cti-v8-arch",
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti.h23 * 0x000 - 0x144: CTI programming and status
24 * 0xEDC - 0xEF8: CTI integration test.
27 /* CTI programming registers */
42 #define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/
43 #define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/
46 #define ITCHOUTACK 0xEEC /* RO CTI CSSoc 400 only*/
47 #define ITTRIGOUTACK 0xEF0 /* RO CTI CSSoc 400 only*/
55 * CTI CSSoc 600 has a max of 32 trigger signals per direction.
56 * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
76 * Trigger connection - connection between a CTI and other (coresight) device
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H A Dcoresight-cti-core.c23 #include "coresight-cti.h"
26 * CTI devices can be associated with a PE, or be connected to CoreSight
36 /* net of CTI devices connected via CTM */
52 * CTI naming. CTI bound to cores will have the name cti_cpu<N> where
56 * CTI device name list - for CTI not bound to cores.
68 /* disable CTI before writing registers */ in cti_write_all_hw_regs()
71 /* write the CTI trigger registers */ in cti_write_all_hw_regs()
83 /* re-enable CTI */ in cti_write_all_hw_regs()
123 /* re-enable CTI on CPU when using CPU hotplug */
174 /* disable CTI */ in cti_disable_hw()
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H A Dcoresight-cti-platform.c12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
17 /* Number of CTI signals in the v8 architecturally defined connection */
22 /* CTI device tree trigger connection node keyword */
25 /* CTI device tree connection property keywords */
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
34 #define CTI_DT_CTM_ID "arm,cti-ctm-id"
38 * CTI can be bound to a CPU, or a system device.
51 /* CTI affinity defaults to no cpu */ in of_cti_get_cpu_at_node()
70 * CTI can be bound to a CPU, or a system device.
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H A DMakefile48 obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
52 coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
53 coresight-cti-sysfs.o
H A DKconfig179 tristate "CoreSight Cross Trigger Interface (CTI) driver"
182 This driver provides support for CoreSight CTI and CTM components.
185 inject events into the trace stream. CTI also provides a software
191 module will be called coresight-cti.
194 bool "Access CTI CoreSight Integration Registers"
199 CTI trigger connections between this and other devices.These
H A Dcoresight-config.h66 * @hw_info: optional hardware device type specific information. (ETM / CTI specific etc)
/linux/Documentation/trace/coresight/
H A Dcoresight-ect.rst4 CoreSight Embedded Cross Trigger (CTI & CTM).
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
21 0 C 0----------->: : +======>(other CTI channel IO)
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
30 The CTI driver enables the programming of the CTI to attach triggers to
34 activating connected output triggers there, unless filtered by the CTI
38 programming registers in the CTI.
53 All the CTI devices are associated with a CTM. On many systems there will be a
57 CTI devices that are interconnected via a given CTM.
62 The CTI devices appear on the existing CoreSight bus alongside the other
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H A Dpanic.rst49 This can be achieved by configuring the comparator, CTI and sink
53 Comparator --->External out --->CTI -->External In---->ETR/ETF stop
120 3. Configure CTI using sysfs interface::
146 ctidevs=`find . -name "cti*"`
155 echo "AP CTI config for $i"
162 echo "ETF CTI config for $i"
169 echo "ETR CTI config for $i"
176 Note: CTI connections are SOC specific and hence the above script is
H A Dcoresight-config.rst19 the cross trigger components such as CTI and CTM. These system settings can
83 specific CTI on the system.
/linux/arch/arm64/boot/dts/qcom/
H A Dqcs615.dtsi1599 cti@6010000 {
1600 compatible = "arm,coresight-cti", "arm,primecell";
1607 cti@6011000 {
1608 compatible = "arm,coresight-cti", "arm,primecell";
1615 cti@6012000 {
1616 compatible = "arm,coresight-cti", "arm,primecell";
1623 cti@6013000 {
1624 compatible = "arm,coresight-cti", "arm,primecell";
1631 cti@6014000 {
1632 compatible = "arm,coresight-cti", "arm,primecell";
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H A Dsm6115.dtsi2100 cti0: cti@8010000 {
2101 compatible = "arm,coresight-cti", "arm,primecell";
2110 cti1: cti@8011000 {
2111 compatible = "arm,coresight-cti", "arm,primecell";
2120 cti2: cti@8012000 {
2121 compatible = "arm,coresight-cti", "arm,primecell";
2130 cti3: cti@8013000 {
2131 compatible = "arm,coresight-cti", "arm,primecell";
2140 cti4: cti@8014000 {
2141 compatible = "arm,coresight-cti", "arm,primecell";
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H A Dmsm8916.dtsi6 #include <dt-bindings/arm/coresight-cti-dt.h>
604 /* CTI 0 - TMC connections */
605 cti0: cti@810000 {
606 compatible = "arm,coresight-cti", "arm,primecell";
615 /* CTI 1 - TPIU connections */
616 cti1: cti@811000 {
617 compatible = "arm,coresight-cti", "arm,primecell";
859 /* CTI - CPU-0 */
860 cti12: cti@858000 {
861 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
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H A Dqcs8300.dtsi2946 cti@4b13000 {
2947 compatible = "arm,coresight-cti", "arm,primecell";
3021 cti@4b8b000 {
3022 compatible = "arm,coresight-cti", "arm,primecell";
3652 cti@682b000 {
3653 compatible = "arm,coresight-cti", "arm,primecell";
3816 cti@68e0000 {
3817 compatible = "arm,coresight-cti", "arm,primecell";
3824 cti@68f0000 {
3825 compatible = "arm,coresight-cti", "arm,primecell";
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/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi292 cti0: cti@22020000 {
293 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
364 cti1: cti@22120000 {
365 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
401 cti2: cti@23020000 {
402 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
485 cti3: cti@23120000 {
486 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
522 cti4: cti@23220000 {
523 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
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H A Djuno-cs-r1r2.dtsi84 cti_sys2: cti@20160000 { /* sys_cti_2 */
85 compatible = "arm,coresight-cti", "arm,primecell";
H A Djuno-r1.dts12 #include <dt-bindings/arm/coresight-cti-dt.h>
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dtrace.json24 …"PublicDescription": "This event is generated each time an event is signaled on CTI output trigger…
28 …"PublicDescription": "This event is generated each time an event is signaled on CTI output trigger…
32 …"PublicDescription": "This event is generated each time an event is signaled on CTI output trigger…
36 …"PublicDescription": "This event is generated each time an event is signaled on CTI output trigger…
/linux/arch/sparc/kernel/
H A Dsyscalls.S218 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
229 bne,pn %icc, linux_syscall_trace32 ! CTI
231 5: call %l7 ! CTI Group brk forced
242 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
253 bne,pn %icc, linux_syscall_trace ! CTI Group
255 2: call %l7 ! CTI Group brk forced
/linux/drivers/media/i2c/
H A Dadv7183_regs.h57 #define ADV7183_CTI_DNR_CTRL_1 0x4D /* CTI DNR ctrl 1 */
58 #define ADV7183_CTI_DNR_CTRL_2 0x4E /* CTI DNR ctrl 2 */
59 #define ADV7183_CTI_DNR_CTRL_4 0x50 /* CTI DNR ctrl 4 */
/linux/drivers/tty/serial/8250/
H A D8250_exar.c179 /* CTI EEPROM offsets */
204 * CTI Serial port line types. These match the values stored in the first
205 * nibble of the CTI EEPROM port_flags word.
617 * Some older CTI cards require MPIO_0 to be set low to enable the
638 * CTI XR17x15X and XR17V25X cards have the serial boards oscillator frequency
663 * CTI xr17c15x and xr17v25x based cards port types are based on PCI IDs.
734 * cti_get_port_type_fpga() - Get the port type of a CTI FPGA card
764 * CTI XR17V35X based cards have the port types stored in the EEPROM.
1429 // Handle CTI FPGA cards in exar_get_nr_ports()
/linux/include/dt-bindings/arm/
H A Dcoresight-cti-dt.h4 * types on CoreSight CTI.
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dst,stih407-irq-syscfg.yaml13 On STi based systems; External, CTI (Core Sight), PMU (Performance

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