| /linux/arch/alpha/kernel/ |
| H A D | core_marvel.c | 171 io7_ioport_csrs *csrs; in io7_clear_errors() local
179 csrs = IO7_CSRS_KERN(io7->pe, port); in io7_clear_errors()
181 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
182 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
183 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors()
184 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
208 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port); in io7_init_hose() local
224 io7_port->csrs = csrs; in io7_init_hose()
265 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose()
266 io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr; in io7_init_hose()
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| H A D | err_marvel.c | 818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
845 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
846 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
847 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
848 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
850 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error()
[all …]
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| /linux/arch/loongarch/include/asm/ |
| H A D | kvm_csr.h | 47 /* Guest CSRS read and write */
152 /* Guest related CSRs */
182 #define kvm_save_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_read(gid))
183 #define kvm_restore_hw_gcsr(csr, gid) (gcsr_write(csr->csrs[gid], gid))
185 #define kvm_read_clear_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_write(0, gid))
191 return csr->csrs[gid]; in kvm_read_sw_gcsr()
196 csr->csrs[gid] = val; in kvm_write_sw_gcsr()
202 csr->csrs[gid] |= val; in kvm_set_sw_gcsr()
210 csr->csrs[gid] &= ~_mask; in kvm_change_sw_gcsr()
211 csr->csrs[gid] |= val & _mask; in kvm_change_sw_gcsr()
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| H A D | kvm_host.h | 146 unsigned long csrs[CSR_MAX_NUMS]; member
193 /* Host CSRs are used when handling exits from guest */
265 return csr->csrs[reg]; in readl_sw_gcsr()
270 csr->csrs[reg] = val; in writel_sw_gcsr()
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| /linux/arch/alpha/include/asm/ |
| H A D | core_t2.h | 60 /* The CSRs below are T3/T4 only */
87 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
91 * | CPU 0 CSRs |
93 * | CPU 1 CSRs |
95 * | CPU 2 CSRs |
97 * | CPU 3 CSRs |
103 * | Mem 0 CSRs |
105 * | Mem 1 CSRs |
107 * | Mem 2 CSRs |
109 * | Mem 3 CSRs |
[all …]
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| /linux/Documentation/devicetree/bindings/net/pcs/ |
| H A D | snps,dw-xpcs.yaml | 21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
49 of the MDIO bus device. If DW XPCS CSRs space is accessed over the
57 so the corresponding subset would be mapped to the lowest 255 CSRs.
65 The way the CSRs are mapped to the memory is platform depended. Since
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-ep.yaml | 47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
73 set of viewport CSRs mapped into the PL space. Note iATU is
79 CSRs mapped in a non-standard base address. The registers offset
86 PCS and PHY CSRs accessible over a dedicated memory mapped
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| H A D | snps,dw-pcie.yaml | 56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
82 set of viewport CSRs mapped into the PL space. Note iATU is
88 CSRs mapped in a non-standard base address. The registers offset
95 PCS and PHY CSRs accessible over a dedicated memory mapped
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| /linux/include/linux/ |
| H A D | litex.h | 4 * helper functions for accessing CSRs.
34 * means that only larger-than-32-bit CSRs will be split across multiple
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| /linux/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| H A D | nfp_arm.h | 145 /* Gasket CSRs */
151 /* BAR CSRs
210 /* MP Core CSRs */
213 /* PL320 CSRs */
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| /linux/arch/riscv/kernel/ |
| H A D | fpu.S | 26 csrs CSR_STATUS, t1
70 csrs CSR_STATUS, t1
127 csrs CSR_STATUS, t1
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| H A D | suspend_entry.S | 44 /* Save CSRs */
82 /* Restore CSRs */
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| H A D | suspend.c | 79 /* Save additional CSRs*/ in cpu_suspend()
107 /* Restore additional CSRs */ in cpu_suspend()
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| H A D | head.S | 397 csrs CSR_STATUS, t1
447 csrs CSR_STATUS, t1
448 csrs CSR_VCSR, x0
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.yaml | 10 RISC-V cores include Control Status Registers (CSRs) which are local to
12 software. Some of these CSRs are used to control local interrupts connected
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| /linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | lmac_common.h | 57 /* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed
158 /* Lock to serialize read/write of global csrs like
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| /linux/drivers/net/ethernet/sfc/falcon/ |
| H A D | io.h | 22 * Many CSRs are very wide and cannot be read or written atomically.
30 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * We also serialise reads from 128-bit CSRs and SRAM with the same
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| /linux/drivers/tty/serial/ |
| H A D | liteuart.c | 23 * CSRs definitions (base address offsets + width)
29 * generic way of indexing the LiteX CSRs.
31 * For more details on how CSRs are defined and handled in LiteX, see comments
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| /linux/drivers/net/ethernet/sfc/siena/ |
| H A D | io.h | 22 * Many CSRs are very wide and cannot be read or written atomically.
30 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * We also serialise reads from 128-bit CSRs and SRAM with the same
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| /linux/Documentation/devicetree/bindings/soc/litex/ |
| H A D | litex,soc-controller.yaml | 13 operations and provide functions for other drivers to read/write CSRs
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| /linux/arch/riscv/lib/ |
| H A D | uaccess.S | 31 csrs CSR_STATUS, t6
224 csrs CSR_STATUS, t6
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| H A D | uaccess_vector.S | 26 csrs CSR_STATUS, t6
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| /linux/drivers/net/ethernet/marvell/octeontx2/nic/ |
| H A D | qos.h | 49 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
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| /linux/arch/riscv/include/asm/ |
| H A D | suspend.h | 45 /* Used to save and restore the CSRs */
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| /linux/arch/loongarch/kvm/ |
| H A D | vcpu.c | 133 * Clear KVM_LARCH_PMU if the guest is not using PMU CSRs when in kvm_lose_pmu()
135 * We don't need to deal with PMU CSRs contexts. in kvm_lose_pmu()
662 * If the PMU CSRs are used, we need to set KVM_REQ_PMU. in _kvm_setcsr()
1570 csr->csrs[LOONGARCH_CSR_GINTC] = 0; in kvm_arch_vcpu_create()
1688 write_csr_gintc(csr->csrs[LOONGARCH_CSR_GINTC]); in _kvm_vcpu_load()
1689 write_csr_gstat(csr->csrs[LOONGARCH_CSR_GSTAT]); in _kvm_vcpu_load()
1785 csr->csrs[LOONGARCH_CSR_GSTAT] = read_csr_gstat(); in _kvm_vcpu_put()
1791 csr->csrs[LOONGARCH_CSR_GINTC] = read_csr_gintc(); in _kvm_vcpu_put()
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