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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-sx93246 SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
19 while CS1 and CS2 are used as shields.
21 [PH1], CS1 is measured, CS0 and CS2 are shield:
23 [PH2], CS2 is measured, CS0 and CS1 are shield:
25 [PH3], CS1 and CS2 are measured (combo mode):
H A Dsysfs-class-watchdog111 chip at CS1.
114 from (CS0->CS1, CS1->CS0) to (CS0->CS0,
115 CS1->CS1).
121 For alternate boot mode (booted from CS1 due to wdt2
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dlantiq,pinctrl-xway.txt55 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
93 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
H A Dmediatek,mt76x8-pinctrl.yaml42 spi, spi cs1, spis, sw_r, uart0, uart1, uart2, utif, wdt,
83 spi cs1, spis, uart0, uart1, uart2, wdt, wled_an,
275 enum: [gpio, refclk, spi cs1]
334 const: spi cs1
338 enum: [spi cs1]
429 enum: [i2c, spi cs1, uart0]
H A Dmarvell,armada-370-pinctrl.txt27 mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
28 sata1(prsnt), spi1(cs1)
70 spi0(cs1)
80 mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
83 pcie(clkreq0), spi1(cs1)
95 mpp64 64 gpio, spi0(miso), spi0(cs1)
H A Dmarvell,armada-38x-pinctrl.txt30 mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq)
39 mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt)
44 mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
73 mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd)
H A Dmarvell,armada-375-pinctrl.txt16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
51 mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
H A Dmarvell,armada-98dx3236-pinctrl.txt18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
46 mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
H A Dmarvell,armada-39x-pinctrl.txt39 mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs),
45 mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
77 mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd)
/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt39 - cs1-used : Have this property if CS1 of this EMIF
41 part attached to CS1, it should be the same type as the one on CS0,
66 cs1-used;
/linux/arch/sh/boards/
H A Dboard-urquell.c35 * CS1 : SRAM, registers, LAN, PCMCIA
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
/linux/sound/soc/intel/catpt/
H A Ddsp.c219 catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val); in catpt_dsp_stall()
221 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_stall()
231 catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val); in catpt_dsp_reset()
233 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_reset()
262 reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS; in catpt_dsp_select_lpclock()
295 catpt_updatel_shim(cdev, CS1, mask, val); in catpt_dsp_select_lpclock()
326 catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT); in catpt_dsp_set_regs_defaults()
363 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in catpt_dsp_power_down()
425 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in catpt_dsp_power_up()
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-fsl-lpspi.yaml61 fsl,spi-only-use-cs1-sel:
64 i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
101 fsl,spi-only-use-cs1-sel;
H A Dmarvell,orion-spi.yaml40 - description: CS1 MBUS target/attribute registers for direct mode
92 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dsemtech,sx9310.yaml56 0 1 - CS0 + CS1
57 1 2 - CS1 + CS2 (default)
58 0 1 2 3 - CS0 + CS1 + CS2 + CS3
/linux/arch/hexagon/include/uapi/asm/
H A Duser.h59 /* cs0 and cs1 are only available with HEXAGON_ARCH_VERSION >= 4 */
61 unsigned long cs1; member
/linux/arch/hexagon/kernel/
H A Dptrace.c65 membuf_store(&to, regs->cs1); in genregs_get()
113 INEXT(&regs->cs1, cs1); in genregs_set()
H A Dsignal.c55 err |= __put_user(regs->cs1, &sc->sc_regs.cs1); in setup_sigcontext()
85 err |= __get_user(regs->cs1, &sc->sc_regs.cs1); in restore_sigcontext()
/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-370.c78 MPP_FUNCTION(0x4, "spi0", "cs1"),
80 MPP_FUNCTION(0x6, "spi1", "cs1")),
255 MPP_FUNCTION(0x5, "spi0", "cs1")),
295 MPP_FUNCTION(0x1, "dev", "cs1"),
307 MPP_FUNCTION(0x6, "spi1", "cs1")),
355 MPP_FUNCTION(0x2, "spi0", "cs1")),
/linux/drivers/watchdog/
H A Daspeed_wdt.c344 * after booting from the alternate chip at CS1.
346 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
351 * both versions of the SoC. For alternate boot mode (booted from CS1 due to
/linux/Documentation/translations/zh_CN/scheduler/
H A Dsched-capacity.rst266 cpusets cs0 cs1
276 mkdir /sys/fs/cgroup/cpuset/cs1
277 echo 2-7 > /sys/fs/cgroup/cpuset/cs1/cpuset.cpus
278 echo 0 > /sys/fs/cgroup/cpuset/cs1/cpuset.mems
/linux/arch/arm/mach-omap2/
H A Dsram242x.S33 mov r12, r2 @ capture CS1 vs CS0
48 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
49 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
71 cmp r12, #0x1 @ normalize if cs1 based
H A Dsram243x.S33 mov r12, r2 @ capture CS1 vs CS0
48 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
49 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
71 cmp r12, #0x1 @ normalize if cs1 based
/linux/drivers/ata/
H A Dpata_octeon_cf.c57 unsigned int cs1; member
170 octeon_cf_set_boot_reg_cfg(cf_port->cs1, div); in octeon_cf_set_piomode()
207 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1), in octeon_cf_set_piomode()
810 void __iomem *cs1 = NULL; in octeon_cf_probe() local
877 cs1 = devm_ioremap(&pdev->dev, res_cs1->start, in octeon_cf_probe()
879 if (!cs1) in octeon_cf_probe()
885 cf_port->cs1 = upper_32_bits(reg); in octeon_cf_probe()
931 ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1; in octeon_cf_probe()
932 ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1; in octeon_cf_probe()

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