Home
last modified time | relevance | path

Searched +full:cs +full:- +full:x (Results 1 – 25 of 647) sorted by relevance

12345678910>>...26

/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_lrc.c1 // SPDX-License-Identifier: MIT
26 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
35 return __vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE); in create_scratch()
57 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
68 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
72 return -ETIME; in wait_for_submit()
81 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
84 u32 *cs; in emit_semaphore_signal() local
90 cs = intel_ring_begin(rq, 4); in emit_semaphore_signal()
91 if (IS_ERR(cs)) { in emit_semaphore_signal()
[all …]
H A Dselftest_workarounds.c1 // SPDX-License-Identifier: MIT
42 err = -EIO; in request_add_sync()
55 err = -ETIMEDOUT; in request_add_spin()
69 wa_init_start(&lists->gt_wa_list, gt, "GT_REF", "global"); in reference_lists_init()
70 gt_init_workarounds(gt, &lists->gt_wa_list); in reference_lists_init()
71 wa_init_finish(&lists->gt_wa_list); in reference_lists_init()
74 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
76 wa_init_start(wal, gt, "REF", engine->name); in reference_lists_init()
81 &lists->engine[id].ctx_wa_list, in reference_lists_init()
93 intel_wa_list_free(&lists->engine[id].wa_list); in reference_lists_fini()
[all …]
H A Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
36 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
40 *cs++ = value; in emit_wait()
41 *cs++ = offset; in emit_wait()
42 *cs++ = 0; in emit_wait()
44 return cs; in emit_wait()
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
49 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in emit_store()
[all …]
H A Dselftest_rps.c1 // SPDX-License-Identifier: MIT
26 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
37 return -1; in cmp_u64()
49 return -1; in cmp_u32()
68 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter() argument
72 u32 *base, *cs; in create_spin_counter() local
76 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
80 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
99 cs = base; in create_spin_counter()
101 *cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2); in create_spin_counter()
[all …]
H A Dintel_ring_submission.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
32 * set-context and then emitting the batch.
42 if (engine->class == RENDER_CLASS) { in set_hwstam()
43 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
57 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
60 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
65 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
68 return sg_page(obj->mm.pages->sgl); in status_page()
85 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
[all …]
H A Dselftest_timeline.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2017-2018 Intel Corporation
29 struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj; in hwsp_page()
32 return sg_page(obj->mm.pages->sgl); in hwsp_page()
39 return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES; in hwsp_cacheline()
49 err = i915_gem_object_lock(tl->hwsp_ggtt->obj, &ww); in selftest_tl_pin()
53 if (err == -EDEADLK) { in selftest_tl_pin()
81 tl = xchg(&state->history[idx], tl); in __mock_hwsp_record()
83 radix_tree_delete(&state->cachelines, hwsp_cacheline(tl)); in __mock_hwsp_record()
96 while (count--) { in __mock_hwsp_timeline()
[all …]
/linux/drivers/net/slip/
H A Dslhc.c21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
43 * - Jan 1995 Bjorn Ekwall
[all …]
/linux/drivers/spi/
H A Dspi-aspeed-smc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2015-2022, IBM Corporation.
15 #include <linux/spi/spi-mem.h>
17 #define DEVICE_NAME "spi-aspeed-smc"
64 u32 cs; member
108 switch (op->data.buswidth) { in aspeed_spi_get_io_mode()
125 ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK; in aspeed_spi_set_io_mode()
127 writel(ctl, chip->ctl); in aspeed_spi_set_io_mode()
133 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE]; in aspeed_spi_start_user()
136 writel(ctl, chip->ctl); in aspeed_spi_start_user()
[all …]
H A Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
32 #include <linux/platform_data/spi-omap2-mcspi.h>
49 /* per-channel banks, 0x14 bytes each, first is: */
56 /* per-register bitmasks: */
92 /* We have 2 DMA channels per CS, one for RX and one for TX */
117 struct list_head cs; member
154 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
161 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
167 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
[all …]
H A Dspi-wpcm-fiu.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/spi/spi-mem.h>
38 #define FIU_UMA_CTS_D_SIZE(x) (x) argument
41 #define FIU_UMA_CTS_CS(x) ((x) << 5) argument
53 /* The memory-mapped view of flash is 16 MiB long */
68 writeb(opcode, fiu->regs + FIU_UMA_CODE); in wpcm_fiu_set_opcode()
73 writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0); in wpcm_fiu_set_addr()
74 writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1); in wpcm_fiu_set_addr()
75 writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2); in wpcm_fiu_set_addr()
83 writeb(data[i], fiu->regs + FIU_UMA_DB0 + i); in wpcm_fiu_set_data()
[all …]
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c1 // SPDX-License-Identifier: MIT
30 static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) in linear_x_y_to_ftiled_pos() argument
53 x *= pixel_size; in linear_x_y_to_ftiled_pos()
56 * F so we can use the Y-tile algorithm to get to that point. in linear_x_y_to_ftiled_pos()
60 x / F_TILE_WIDTH * 4096; in linear_x_y_to_ftiled_pos()
63 tile_x = x % F_TILE_WIDTH; in linear_x_y_to_ftiled_pos()
86 CLIENT_TILING_Y, /* Y-major, either Tile4 (Xe_HP and beyond) or legacy TileY */
114 /* XY_FAST_COPY_BLT does not exist on pre-gen9 platforms */ in fastblit_supports_x_tiling()
115 drm_WARN_ON(&i915->drm, gen < 9); in fastblit_supports_x_tiling()
128 /* XY_FAST_COPY_BLT does not exist on pre-gen9 platforms */ in fast_blit_ok()
[all …]
/linux/drivers/scsi/
H A Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
[all …]
/linux/drivers/mtd/nand/raw/
H A Drenesas-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Evatronix/Renesas R-Car Gen3, RZ/N1D, RZ/N1S, RZ/N1L NAND controller driver
11 #include <linux/dma-mapping.h>
23 #define COMMAND_SEQ(x) FIELD_PREP(GENMASK(5, 0), (x)) argument
36 #define COMMAND_0(x) FIELD_PREP(GENMASK(15, 8), (x)) argument
37 #define COMMAND_1(x) FIELD_PREP(GENMASK(23, 16), (x)) argument
38 #define COMMAND_2(x) FIELD_PREP(GENMASK(31, 24), (x)) argument
42 #define CONTROL_ECC_BLOCK_SIZE(x) FIELD_PREP(GENMASK(2, 1), (x)) argument
48 #define CONTROL_BLOCK_SIZE(x) FIELD_PREP(GENMASK(7, 6), (x)) argument
55 #define MEM_RDY(cs, reg) (FIELD_GET(GENMASK(3, 0), (reg)) & BIT(cs)) argument
[all …]
/linux/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
176 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
177 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
178 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
179 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
188 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
212 u32 *cs; in restore_context_mmio_for_inhibit() local
215 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
216 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
217 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; in restore_context_mmio_for_inhibit()
[all …]
/linux/Documentation/scsi/
H A DNinjaSCSI.rst1 .. SPDX-License-Identifier: GPL-2.0
4 WorkBiT NinjaSCSI-3/32Bi driver for Linux
10 This is Workbit corp.'s(http://www.workbit.co.jp/) NinjaSCSI-3
17 :pcmcia-cs: 3.1.27
18 :gcc: gcc-2.95.4
19 :PC card: I-O data PCSC-F (NinjaSCSI-3),
20 I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi)
21 :SCSI device: I-O data CDPS-PX24 (CD-ROM drive),
22 Media Intelligent MMO-640GT (Optical disk drive)
27 (a) Check your PC card is true "NinjaSCSI-3" card.
[all …]
/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_cmd.c1 // SPDX-License-Identifier: MIT
23 static u32 *pxp_emit_session_selection(u32 *cs, u32 idx) in pxp_emit_session_selection() argument
25 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
28 *cs++ = MI_FLUSH_DW; in pxp_emit_session_selection()
29 *cs++ = 0; in pxp_emit_session_selection()
30 *cs++ = 0; in pxp_emit_session_selection()
33 *cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx); in pxp_emit_session_selection()
35 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
38 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN | in pxp_emit_session_selection()
40 *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT; in pxp_emit_session_selection()
[all …]
/linux/drivers/ps3/
H A Dps3av_cmd.c1 // SPDX-License-Identifier: GPL-2.0-only
28 int cs; member
33 .cs = PS3AV_CMD_VIDEO_CS_RGB_8,
37 .cs = PS3AV_CMD_VIDEO_CS_RGB_10,
41 .cs = PS3AV_CMD_VIDEO_CS_RGB_12,
45 .cs = PS3AV_CMD_VIDEO_CS_YUV444_8,
49 .cs = PS3AV_CMD_VIDEO_CS_YUV444_10,
53 .cs = PS3AV_CMD_VIDEO_CS_YUV444_12,
57 .cs = PS3AV_CMD_VIDEO_CS_YUV422_8,
61 .cs = PS3AV_CMD_VIDEO_CS_YUV422_10,
[all …]
/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
21 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) argument
22 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) argument
27 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) argument
30 #define FMC2_CIDCFGR(x) ((x) * 0x8 + FMC2_CIDCFGR0) argument
32 #define FMC2_SEMCR(x) ((x) * 0x8 + FMC2_SEMCR0) argument
68 #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) argument
210 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
234 const struct stm32_fmc2_prop *prop, int cs);
235 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
[all …]
H A Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
83 struct device_node *np, u32 cs) in pl172_setup_static() argument
90 if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) { in pl172_setup_static()
[all …]
/linux/drivers/media/v4l2-core/
H A Dv4l2-ctrls-api.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2021 Hans Verkuil <hverkuil-cisco@xs4all.nl>
8 #define pr_fmt(fmt) "v4l2-ctrls: " fmt
13 #include <media/v4l2-ctrls.h>
14 #include <media/v4l2-dev.h>
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-event.h>
17 #include <media/v4l2-ioctl.h>
19 #include "v4l2-ctrls-priv.h"
46 if (ctrl->is_ptr && !ctrl->is_string) in ptr_to_user()
[all …]
/linux/arch/powerpc/include/asm/
H A Dmpc5121.h1 /* SPDX-License-Identifier: GPL-2.0-only */
50 u32 cs_cfg[8]; /* CS config */
51 u32 cs_ctrl; /* CS Control Register */
52 u32 cs_status; /* CS Status Register */
53 u32 burst_ctrl; /* CS Burst Control Register */
54 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
55 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
59 int mpc512x_cs_config(unsigned int cs, u32 val);
82 #define MPC512X_SCLPC_CS(x) (((x) & 0x7) << 24) argument
86 #define MPC512X_SCLPC_BPT(x) ((x) & 0x3f) argument
[all …]
/linux/drivers/clocksource/
H A Dtimer-sun5i.c1 // SPDX-License-Identifier: GPL-2.0
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
45 #define nb_to_sun5i_timer(x) \ argument
46 container_of(x, struct sun5i_timer, clk_rate_cb)
47 #define clksrc_to_sun5i_timer(x) \ argument
48 container_of(x, struct sun5i_timer, clksrc)
49 #define clkevt_to_sun5i_timer(x) \ argument
50 container_of(x, struct sun5i_timer, clkevt)
60 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
62 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
[all …]
/linux/drivers/edac/
H A Darmada_xp_edac.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <asm/hardware/cache-l2x0.h>
13 #include <asm/hardware/cache-aurora-l2.h>
29 #define SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs) (20+cs) argument
30 #define SDRAM_ADDR_CTRL_SIZE_HIGH_MASK(cs) (0x1 << SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs)) argument
31 #define SDRAM_ADDR_CTRL_ADDR_SEL_MASK(cs) BIT(16+cs) argument
32 #define SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs) (cs*4+2) argument
33 #define SDRAM_ADDR_CTRL_SIZE_LOW_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs)) argument
34 #define SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs) (cs*4) argument
35 #define SDRAM_ADDR_CTRL_STRUCT_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs)) argument
[all …]
/linux/tools/testing/selftests/x86/
H A Dsigreturn.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sigreturn.c - tests for x86 sigreturn(2) and exit-to-userspace
4 * Copyright (c) 2014-2015 Andrew Lutomirski
9 * For now, this focuses on the effects of unusual CS and SS values,
60 * UC_SIGCONTEXT_SS will be set when delivering 64-bit or x32 signals on
66 * when delivering a signal that came from 64-bit code.
71 * saved CS is not 64-bit)
74 * new SS = a flat 32-bit data segment
82 * Illumos "LX branded zones"). Solaris-based kernels reserve LDT
83 * entries 0-5 for their own internal purposes, so start our LDT
[all …]

12345678910>>...26