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/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
40 #define FMC2_BCR_MUXEN BIT(1)
76 #define FMC2_SR_ISOST GENMASK(1, 0)
80 #define FMC2_CIDCFGR_SEMEN BIT(1)
91 #define FMC2_CID1 1
136 FMC2_REG_BCR = 1,
173 FMC2_CSCOUNT_1 = 1,
210 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
234 const struct stm32_fmc2_prop *prop, int cs);
235 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
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H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
81 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
97 * The first 1MB of GPMC address space is typically mapped to
139 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
140 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
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/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
20 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
H A Dgen8_engine_cs.c1 // SPDX-License-Identifier: MIT
18 u32 *cs, flags = 0; in gen8_emit_flush_rcs()
44 if (GRAPHICS_VER(rq->i915) == 9) in gen8_emit_flush_rcs()
48 if (IS_KABYLAKE(rq->i915) && IS_GRAPHICS_STEP(rq->i915, 0, STEP_C0)) in gen8_emit_flush_rcs()
60 cs = intel_ring_begin(rq, len); in gen8_emit_flush_rcs()
61 if (IS_ERR(cs)) in gen8_emit_flush_rcs()
62 return PTR_ERR(cs); in gen8_emit_flush_rcs()
65 cs in gen8_emit_flush_rcs()
16 u32 *cs, flags = 0; gen8_emit_flush_rcs() local
81 u32 cmd, *cs; gen8_emit_flush_xcs() local
115 u32 *cs; gen11_emit_flush_rcs() local
137 u32 *cs; gen11_emit_flush_rcs() local
199 gen12_emit_aux_table_inv(struct intel_engine_cs * engine,u32 * cs) gen12_emit_aux_table_inv() argument
228 u32 *cs; mtl_dummy_pipe_control() local
256 u32 *cs; gen12_emit_flush_rcs() local
311 u32 *cs, count; gen12_emit_flush_rcs() local
365 u32 *cs; gen12_emit_flush_xcs() local
436 u32 *cs; gen8_emit_init_breadcrumb() local
488 u32 *cs; __xehp_emit_bb_start() local
540 u32 *cs; gen8_emit_bb_start_noarb() local
576 u32 *cs; gen8_emit_bb_start() local
613 gen8_emit_wa_tail(struct i915_request * rq,u32 * cs) gen8_emit_wa_tail() argument
626 emit_preempt_busywait(struct i915_request * rq,u32 * cs) emit_preempt_busywait() argument
642 gen8_emit_fini_breadcrumb_tail(struct i915_request * rq,u32 * cs) gen8_emit_fini_breadcrumb_tail() argument
657 emit_xcs_breadcrumb(struct i915_request * rq,u32 * cs) emit_xcs_breadcrumb() argument
662 gen8_emit_fini_breadcrumb_xcs(struct i915_request * rq,u32 * cs) gen8_emit_fini_breadcrumb_xcs() argument
667 gen8_emit_fini_breadcrumb_rcs(struct i915_request * rq,u32 * cs) gen8_emit_fini_breadcrumb_rcs() argument
687 gen11_emit_fini_breadcrumb_rcs(struct i915_request * rq,u32 * cs) gen11_emit_fini_breadcrumb_rcs() argument
727 gen12_emit_preempt_busywait(struct i915_request * rq,u32 * cs) gen12_emit_preempt_busywait() argument
755 hold_switchout_emit_wa_busywait(struct i915_request * rq,u32 * cs) hold_switchout_emit_wa_busywait() argument
784 gen12_emit_fini_breadcrumb_tail(struct i915_request * rq,u32 * cs) gen12_emit_fini_breadcrumb_tail() argument
805 gen12_emit_fini_breadcrumb_xcs(struct i915_request * rq,u32 * cs) gen12_emit_fini_breadcrumb_xcs() argument
812 gen12_emit_fini_breadcrumb_rcs(struct i915_request * rq,u32 * cs) gen12_emit_fini_breadcrumb_rcs() argument
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H A Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
31 return (a[1] + 2 * a[2] + a[3]) >> 2; in trifilter()
34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
36 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
40 *cs++ = value; in emit_wait()
41 *cs++ = offset; in emit_wait()
42 *cs++ = 0; in emit_wait()
44 return cs; in emit_wait()
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
[all …]
H A Dgen8_engine_cs.h1 /* SPDX-License-Identifier: MIT */
43 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
44 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
46 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
47 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
48 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
50 u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs);
59 batch[1] = bit_group_1; in __gen8_emit_pipe_control()
79 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1) in __gen8_emit_write_rcs() argument
81 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_write_rcs()
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
17 0: Asynchronous mode 1 SRAM/FRAM.
18 1: Asynchronous mode 1 PSRAM.
33 st,fmc2-ebi-cs-cclk-enable:
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/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
23 static void clocksource_enqueue(struct clocksource *cs);
25 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
27 u64 delta = clocksource_delta(end, start, cs->mask, cs->max_raw_delta); in cycles_to_nsec_safe()
29 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
30 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
32 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
36 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
47 * NSEC_PER_SEC == 1GHz and @from is the counter frequency. For clock
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/linux/arch/m68k/include/asm/
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
59 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
[all …]
H A Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
58 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
[all …]
H A Dm5206sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
26 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
58 #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
59 #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
60 #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
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/linux/drivers/accel/habanalabs/common/
H A Dhw_queue.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
13 * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
23 ptr &= ((HL_QUEUE_LENGTH << 1) - 1); in hl_hw_queue_add_ptr()
28 return atomic_read(ci) & ((queue_len << 1) - 1); in queue_ci_get()
33 int delta = (q->pi - queue_ci_get(&q->ci, queue_len)); in queue_free_slots()
36 return (queue_len - delta); in queue_free_slots()
38 return (abs(delta) - queue_len); in queue_free_slots()
41 void hl_hw_queue_update_ci(struct hl_cs *cs) in hl_hw_queue_update_ci() argument
43 struct hl_device *hdev = cs->ctx->hdev; in hl_hw_queue_update_ci()
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/linux/tools/perf/util/
H A Dcomm.c1 // SPDX-License-Identifier: GPL-2.0
24 static void comm_strs__remove_if_last(struct comm_str *cs);
44 static refcount_t *comm_str__refcnt(struct comm_str *cs) in comm_str__refcnt() argument
46 return &RC_CHK_ACCESS(cs)->refcnt; in comm_str__refcnt()
49 static const char *comm_str__str(const struct comm_str *cs) in comm_str__str() argument
51 return &RC_CHK_ACCESS(cs)->str[0]; in comm_str__str()
54 static struct comm_str *comm_str__get(struct comm_str *cs) in comm_str__get() argument
58 if (RC_CHK_GET(result, cs)) in comm_str__get()
59 refcount_inc_not_zero(comm_str__refcnt(cs)); in comm_str__get()
64 static void comm_str__put(struct comm_str *cs) in comm_str__put() argument
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/linux/fs/fuse/
H A Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
45 return time_is_before_jiffies(req->create_time + fc->timeout.req_timeout); in fuse_request_expired()
62 * - check the fiq pending list
63 * - check the bg queue
64 * - check the fpq io and processing lists
69 * between lists, re-sent requests at the head of the pending list having a
78 struct fuse_iqueue *fiq = &fc->iq; in fuse_check_timeout()
83 if (!atomic_read(&fc->num_waiting)) in fuse_check_timeout()
86 spin_lock(&fiq->lock); in fuse_check_timeout()
87 expired = fuse_request_expired(fc, &fiq->pending); in fuse_check_timeout()
[all …]
/linux/kernel/cgroup/
H A Dcpuset-v1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 #include "cgroup-internal.h"
4 #include "cpuset-internal.h"
11 struct cpuset *cs; member
15 * Frequency meter - How fast is some event occurring?
19 * fmeter_init() - initialize a frequency meter.
20 * fmeter_markevent() - called each time the event happens.
21 * fmeter_getrate() - returns the recent rate of such events.
22 * fmeter_update() - internal routine used to update fmeter.
29 * The filter is single-pole low-pass recursive (IIR). The time unit
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H A Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
24 #include "cpuset-internal.h"
50 * node binding, add this key to provide a quick low-cost judgment
74 * Exclusive CPUs distributed out to local or remote sub-partitions of
100 * - update_partition_sd_lb()
101 * - update_cpumasks_hier()
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/linux/drivers/spi/
H A Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
32 #include <linux/platform_data/spi-omap2-mcspi.h>
49 /* per-channel banks, 0x14 bytes each, first is: */
56 /* per-register bitmasks: */
64 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
83 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92 /* We have 2 DMA channels per CS, one for RX and one for TX */
117 struct list_head cs; member
133 unsigned int pin_dir:1;
[all …]
H A Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
24 #include "spi-dw.h"
39 #define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
41 #define MSCC_IF_SI_OWNER_SIBM 1
57 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
58 * gpios for cs 2,3 as defined in the device tree.
60 * cs: | 1 0
61 * bit: |---3-------2-------1-------0
65 #define ELBA_SPICS_OFFSET(cs) ((cs) << 1) argument
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H A Dspi-xlp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2003-2015 Broadcom Corporation
17 #define XLP_SPI_CPOL BIT(1)
40 #define XLP_SPI_XFR_DONE BIT(1)
50 #define XLP_SPI_INTR_TXTH BIT(1)
73 #define XLP_SPI_SYS_CLKDIS BIT(1)
98 int cs; /* target device chip select */ member
100 bool cmd_cont; /* cs active */
105 int cs, int regoff) in xlp_spi_reg_read() argument
107 return readl(priv->base + regoff + cs * SPI_CS_OFFSET); in xlp_spi_reg_read()
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/linux/drivers/net/slip/
H A Dslhc.c21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
43 * - Jan 1995 Bjorn Ekwall
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Ddata-fabric.json4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
7 "PerPkg": "1",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
15 "PerPkg": "1",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
23 "PerPkg": "1",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
31 "PerPkg": "1",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
39 "PerPkg": "1",
[all …]
/linux/drivers/clocksource/
H A Dem_sti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
61 iowrite32(value, p->base + offs); in em_sti_write()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
84 em_sti_write(p, STI_CONTROL, 1); in em_sti_enable()
95 clk_disable(p->clk); in em_sti_disable()
103 /* the STI hardware buffers the 48-bit count, but to in em_sti_count()
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/linux/include/linux/
H A Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
49 * @archdata: Optional arch-specific data
60 * 1-99: Unfit for real use
62 * 100-199: Base level usability.
64 * 200-299: Good.
66 * 300-399: Desired.
68 * 400-499: Perfect
69 * The ideal clocksource. A must-use where
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/linux/fs/fat/
H A Dfat_test.c1 // SPDX-License-Identifier: GPL-2.0
17 /* With 3-letter extension. */ in fat_checksum_test()
19 /* With short (1-letter) extension. */ in fat_checksum_test()
28 u8 cs; member
34 .name = "Earliest possible UTC (1980-01-01 00:00:00)",
38 .cs = 0,
42 .name = "Latest possible UTC (2107-12-31 23:59:58)",
46 .cs = 0,
50 .name = "Earliest possible (UTC-11) (== 1979-12-31 13:00:00 UTC)",
54 .cs = 0,
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