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/linux/tools/testing/selftests/kvm/s390x/
H A Dresets.c27 /* set several CRs to "safe" value */ in guest_code_initial()
137 TEST_ASSERT(sregs.crs[0] == 0xE0UL, "cr0 == 0xE0 (KVM_GET_SREGS)"); in assert_initial()
138 TEST_ASSERT(sregs.crs[14] == 0xC2000000UL, in assert_initial()
140 TEST_ASSERT(!memcmp(&sregs.crs[1], regs_null, sizeof(sregs.crs[1]) * 12), in assert_initial()
142 TEST_ASSERT(sregs.crs[15] == 0, "cr15 == 0 (KVM_GET_SREGS)"); in assert_initial()
145 TEST_ASSERT(sync_regs->crs[0] == 0xE0UL, "cr0 == 0xE0 (sync_regs)"); in assert_initial()
146 TEST_ASSERT(sync_regs->crs[14] == 0xC2000000UL, in assert_initial()
148 TEST_ASSERT(!memcmp(&sync_regs->crs[1], regs_null, 8 * 12), in assert_initial()
150 TEST_ASSERT(sync_regs->crs[15] == 0, "cr15 == 0 (sync_regs)"); in assert_initial()
176 TEST_ASSERT(sync_regs->crs[2] == 0x10, "cr2 == 10 (sync_regs)"); in assert_normal_noclear()
[all …]
H A Dtprot.c233 run->s.regs.crs[0] |= CR0_FETCH_PROTECTION_OVERRIDE; in main()
237 run->s.regs.crs[0] |= CR0_STORAGE_PROTECTION_OVERRIDE; in main()
H A Dmemop.c736 t.run->s.regs.crs[0] |= CR0_STORAGE_PROTECTION_OVERRIDE; in test_copy_key_storage_prot_override()
847 t.run->s.regs.crs[0] |= CR0_STORAGE_PROTECTION_OVERRIDE; in test_errors_key_storage_prot_override()
891 t.run->s.regs.crs[0] |= CR0_FETCH_PROTECTION_OVERRIDE; in test_copy_key_fetch_prot_override()
950 t.run->s.regs.crs[0] |= CR0_FETCH_PROTECTION_OVERRIDE; in test_errors_key_fetch_prot_override_enabled()
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h140 #define B43_NPHY_CRS_THRES1 B43_PHY_N(0x044) /* CRS threshold 1 */
141 #define B43_NPHY_CRS_THRES2 B43_PHY_N(0x045) /* CRS threshold 2 */
142 #define B43_NPHY_CRS_THRES3 B43_PHY_N(0x046) /* CRS threshold 3 */
143 #define B43_NPHY_CRSCTL B43_PHY_N(0x047) /* CRS control */
442 #define B43_NPHY_CRSIT_COCNT_LO B43_PHY_N(0x124) /* CRS idle time CRS-on count (low) */
443 #define B43_NPHY_CRSIT_COCNT_HI B43_PHY_N(0x125) /* CRS idle time CRS-on count (high) */
444 #define B43_NPHY_CRSIT_MTCNT_LO B43_PHY_N(0x126) /* CRS idle time measure time count (low) */
445 #define B43_NPHY_CRSIT_MTCNT_HI B43_PHY_N(0x127) /* CRS idle time measure time count (high) */
466 #define B43_NPHY_MIMO_CRSTXEXT B43_PHY_N(0x13A) /* MIMO PHY CRS TX extension */
607 #define B43_NPHY_CRS_CHECK B43_PHY_N(0x1CB) /* CRS check */
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H A Dphy_a.h14 #define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
58 #define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */
59 #define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */
H A Dphy_lp.h13 #define B43_LPPHY_B_CRS_THRESH B43_PHY_CCK(0x06) /* B PHY CRS Thresh */
140 #define B43_LPPHY_CRS_ED_THRESH B43_PHY_OFDM(0x32) /* crs ed thresh */
178 #define B43_LPPHY_PHY_CRS_ENABLE_ADDR B43_PHY_OFDM(0x58) /* phy CRS Enable Address */
180 #define B43_LPPHY_IDLETIME_CRS_ON_LO B43_PHY_OFDM(0x5A) /* Idletime CRS On Lo */
181 #define B43_LPPHY_IDLETIME_CRS_ON_HI B43_PHY_OFDM(0x5B) /* Idletime CRS On Hi */
186 #define B43_LPPHY_REG_CRS_ENABLE B43_PHY_OFDM(0x60) /* reg crs enable */
193 #define B43_LPPHY_HOLD_CRS_ON_VAL B43_PHY_OFDM(0x67) /* hold CRS On Value */
194 #define B43_LPPHY_OFDM_TX_PHY_CRS_DELAY_VAL B43_PHY_OFDM(0x69) /* ofdm tx phy CRS Delay Value */
195 #define B43_LPPHY_CCK_TX_PHY_CRS_DELAY_VAL B43_PHY_OFDM(0x6A) /* cck tx phy CRS Delay Value */
198 #define B43_LPPHY_PHY_CRS_OFFSET_TIMER_VAL B43_PHY_OFDM(0x6D) /* phy CRS offset Timer Value */
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dbranch.json48 ….This event counts when any procedure return which can be predicted by the CRS is retired, was tak…
51 ….This event counts when any procedure return which can be predicted by the CRS is retired, was tak…
54 ….This event counts when any procedure return which can be predicted by the CRS is retired, was tak…
57 ….This event counts when any procedure return which can be predicted by the CRS is retired, was tak…
/linux/tools/testing/selftests/kvm/x86_64/
H A Dxen_shinfo_test.c1082 struct compat_vcpu_runstate_info *crs; in main() local
1087 crs = (void *)rs; in main()
1105 TEST_ASSERT(crs->state == rst.u.runstate.state, "Runstate mismatch"); in main()
1106 TEST_ASSERT(crs->state_entry_time == rst.u.runstate.state_entry_time, in main()
1108 TEST_ASSERT(crs->time[RUNSTATE_running] == rst.u.runstate.time_running, in main()
1110 TEST_ASSERT(crs->time[RUNSTATE_runnable] == rst.u.runstate.time_runnable, in main()
1112 TEST_ASSERT(crs->time[RUNSTATE_blocked] == rst.u.runstate.time_blocked, in main()
1114 TEST_ASSERT(crs->time[RUNSTATE_offline] == rst.u.runstate.time_offline, in main()
1116 TEST_ASSERT(crs->time[RUNSTATE_offline + 1] == 0xa5a5a5a5a5a5a5a5ULL, in main()
1118 TEST_ASSERT(crs->state_entry_time == crs->time[0] + in main()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt35 mii(crs)
43 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
73 mii(crs), sata0(prsnt)
81 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
117 mii(crs), sata0(prsnt)
125 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
166 mii(crs), sata0(prsnt)
174 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
228 mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
238 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
H A Dmarvell,orion-pinctrl.txt34 mpp10 10 gpio, ge(crs)
59 mpp10 10 gpio, ge(crs)
84 mpp10 10 gpio, ge(crs)
H A Dmarvell,armada-370-pinctrl.txt47 mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
H A Dmarvell,armada-xp-pinctrl.txt40 mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
/linux/tools/testing/selftests/kvm/include/s390x/
H A Ddebug_print.h66 print_hex_bytes("CRS", (u64)sync_regs->crs, 8 * NUM_CRS); in print_regs()
/linux/drivers/iommu/
H A Domap-iommu-debug.c113 __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) in __dump_tlb_entries() argument
118 struct cr_regs *p = crs; in __dump_tlb_entries()
132 return p - crs; in __dump_tlb_entries()
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dphy.h109 #define B43legacy_PHY_CRSTHRES1 B43legacy_PHY_OFDM(0x06) /* CRS Threshold 1 */
144 #define B43legacy_PHY_CRSTHRES1_R1 B43legacy_PHY_OFDM(0xC0) /* CRS Threshold 1 (rev 1 only) */
145 #define B43legacy_PHY_CRSTHRES2_R1 B43legacy_PHY_OFDM(0xC1) /* CRS Threshold 2 (rev 1 only) */
/linux/include/video/
H A Dgbe.h39 volatile uint32_t crs_start_xy; /* eol/f crs/xy reset val */
66 volatile uint32_t crs_cmap[3]; /* crs cmap */
68 volatile uint32_t crs_glyph[64];/* crs glyph */
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrochip,ksz.yaml71 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
78 COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.
/linux/tools/testing/selftests/kvm/lib/s390x/
H A Dprocessor.c186 sregs.crs[0] |= 0x00040000; /* Enable floating point regs */ in vm_arch_vcpu_add()
187 sregs.crs[1] = vm->pgd | 0xf; /* Primary region table */ in vm_arch_vcpu_add()
/linux/arch/parisc/kernel/
H A Dreal2.S85 /* restore CRs before going virtual in case we page fault */
263 /* restore CRs before going virtual in case we page fault */
/linux/drivers/platform/x86/amd/hsmp/
H A Dacpi.c187 dev_err(sock->dev, "Failed to look up MP1 base address from CRS method, err: %s\n", in hsmp_read_acpi_crs()
219 /* Read MP1 base address from CRS method */ in hsmp_parse_acpi_table()
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-boneblack.dts140 "[mii crs]",
/linux/arch/powerpc/boot/dts/
H A Dmpc832x_rdb.dts194 0 31 2 0 1 0>; /* CRS */
214 1 13 2 0 1 0>; /* CRS */
/linux/drivers/misc/cxl/
H A Dsysfs.c666 list_for_each_entry_safe(cr, tmp, &afu->crs, list) { in cxl_sysfs_afu_remove()
678 INIT_LIST_HEAD(&afu->crs); in cxl_sysfs_afu_add()
713 list_add(&cr->list, &afu->crs); in cxl_sysfs_afu_add()
/linux/tools/arch/s390/include/uapi/asm/
H A Dkvm.h514 __u64 crs[16];
581 __u64 crs[16]; /* control registers */
513 __u64 crs[16]; global() member
580 __u64 crs[16]; /* control registers */ global() member
/linux/Documentation/virt/kvm/s390/
H A Ds390-pv.rst58 indicating that the contents of CRs 0, 6, or 14 have been changed,

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