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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dqcom,cpucp-mbox.yaml4 $id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
7 title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
13 The CPUSS Control Processor (CPUCP) mailbox controller enables communication
14 between AP and CPUCP by acting as a doorbell between them.
19 - const: qcom,x1e80100-cpucp-mbox
23 - description: CPUCP rx register region
24 - description: CPUCP tx register region
45 compatible = "qcom,x1e80100-cpucp-mbox";
/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dqcom,osm-l3.yaml33 - qcom,sm6375-cpucp-l3
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdx75.dtsi303 cpucp_fw_mem: cpucp-fw@87c00000 {
H A Dqdu1000.dtsi278 cpucp_fw_mem: cpucp-fw@80b00000 {
H A Dsm6375.dtsi1815 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
H A Dsa8775p.dtsi548 cpucp_backup_mem: cpucp-backup@91b40000 {
694 cpucp_fw_mem: cpucp-fw@db200000 {
H A Dx1e80100.dtsi447 cpucp_log_mem: cpucp-log@80e00000 {
452 cpucp_mem: cpucp@80e40000 {
H A Dsm8550.dtsi609 cpucp_fw_mem: cpucp-fw-region@d8140000 {
H A Dsc7280.dtsi137 cpucp_mem: cpucp@80b00000 {