| /linux/arch/mips/kernel/ |
| H A D | cacheinfo.c | 60 int cpu1; in fill_cpumask_siblings() local
62 for_each_possible_cpu(cpu1) in fill_cpumask_siblings()
63 if (cpus_are_siblings(cpu, cpu1)) in fill_cpumask_siblings()
64 cpumask_set_cpu(cpu1, cpu_map); in fill_cpumask_siblings()
69 int cpu1; in fill_cpumask_cluster() local
72 for_each_possible_cpu(cpu1) in fill_cpumask_cluster()
73 if (cpu_cluster(&cpu_data[cpu1]) == cluster) in fill_cpumask_cluster()
74 cpumask_set_cpu(cpu1, cpu_map); in fill_cpumask_cluster()
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| H A D | bmips_vec.S | 32 * Alternate CPU1 startup vector for BMIPS4350
34 * On some systems the bootloader has already started CPU1 and configured
54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
87 /* if the NMI bit is clear, assume this is a CPU1 reset instead */
167 * CPU1 reset vector (used for the initial boot only)
190 /* initialize CPU1's local I-cache */
251 * CPU1 warm restart vector (used for second and subsequent boots).
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| /linux/tools/memory-model/Documentation/ |
| H A D | locking.txt | 35 void CPU1(void)
43 The basic rule guarantees that if CPU0() acquires mylock before CPU1(),
67 void CPU1(void)
76 mylock before CPU1(), then both r0 and r1 must be set to the value 0.
108 /* CPU1() is the exactly the same as CPU0(). */
133 /* CPU1() is the exactly the same as CPU0(). */
163 void CPU1(void)
196 void CPU1(void)
241 void CPU1(void)
254 CPU0() sets it to "1" while holding the lock, and CPU1() emulates the
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| H A D | recipes.txt | 81 void CPU1(void)
89 The basic rule guarantees that if CPU0() acquires mylock before CPU1(),
107 void CPU1(void)
116 mylock before CPU1(), then both r0 and r1 must be set to the value 0.
138 void CPU1(void)
171 void CPU1(void)
226 void CPU1(void)
261 void CPU1(void)
303 void CPU1(void)
371 void CPU1(void)
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| /linux/arch/arm/mach-omap2/ |
| H A D | omap-smp.c | 149 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. in omap4_secondary_init()
151 * init and for CPU1, a secure PPA API provided. CPU0 must be ON in omap4_secondary_init()
152 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. in omap4_secondary_init()
201 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to in omap4_boot_secondary()
206 * 4.3.4.2 Power States of CPU0 and CPU1 in omap4_boot_secondary()
216 * Because the ROM Code is based on the r1pX GIC, the CPU1 in omap4_boot_secondary()
219 * 1) Before doing the CPU1 wakeup, CPU0 must disable in omap4_boot_secondary()
221 * 2) CPU1 must re-enable the GIC distributor on in omap4_boot_secondary()
302 * We may need to reset CPU1 before configuring, otherwise kexec boot can end
304 * occasionally fail to bring up CPU1 on 4430 if CPU1 fails to enter deeper
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| H A D | cpuidle44xx.c | 128 * CPU0 has to wait and stay ON until CPU1 is OFF state. in omap_enter_idle_coupled()
130 * of triggeing all the possible low power modes once CPU1 is in omap_enter_idle_coupled()
138 * CPU1 could have already entered & exited idle in omap_enter_idle_coupled()
142 * waiting for CPU1 off. in omap_enter_idle_coupled()
190 /* Wakeup CPU1 only if it is not offlined */ in omap_enter_idle_coupled()
239 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
247 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
257 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
276 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
284 /* C2 - CPU0 RET + CPU1 RET + MPU CSWR */
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| H A D | omap-mpuss-lowpower.c | 10 * CPU0 and CPU1 LPRM modules.
11 * CPU0, CPU1 and MPUSS each have there own power domain and
14 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
23 * CPU0 CPU1 MPUSS
115 * Program the wakeup routine address for the CPU0 and CPU1
413 pr_err("Lookup failed for CPU1 pwrdm\n"); in omap4_mpuss_init()
421 /* Initialise CPU1 power domain state to ON */ in omap4_mpuss_init()
467 * wake CPU1 and cause a hang.
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5422-odroidhc1.dts | 62 <&cpu1 0 2>,
78 <&cpu1 3 8>,
88 cpu1_thermal: cpu1-thermal {
111 <&cpu1 0 2>,
122 <&cpu1 3 8>,
155 <&cpu1 0 2>,
166 <&cpu1 3 8>,
199 <&cpu1 0 2>,
210 <&cpu1 3 8>,
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| H A D | exynos5420-arndale-octa.dts | 108 <&cpu1 0 2>,
124 <&cpu1 3 6>,
140 <&cpu1 6 11>,
179 <&cpu1 0 2>,
191 <&cpu1 3 6>,
203 <&cpu1 6 11>,
242 <&cpu1 0 2>,
254 <&cpu1 3 6>,
266 <&cpu1 6 11>,
305 <&cpu1 0 2>,
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| H A D | exynos5422-odroidxu3-lite.dts | 53 <&cpu1 3 7>,
64 <&cpu1 3 7>,
75 <&cpu1 3 7>,
86 <&cpu1 3 7>,
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| H A D | exynos5422-odroidxu3-common.dtsi | 113 <&cpu1 0 2>,
129 <&cpu1 3 8>,
139 cpu1_thermal: cpu1-thermal {
191 <&cpu1 0 2>,
202 <&cpu1 3 8>,
264 <&cpu1 0 2>,
275 <&cpu1 3 8>,
337 <&cpu1 0 2>,
348 <&cpu1 3 8>,
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| /linux/Documentation/translations/zh_CN/scheduler/ |
| H A D | sched-capacity.rst | 62 - work_per_hz(CPU1) = W/2
68 - capacity(CPU1) = C/2
79 CPU1 work ^
94 - max_freq(CPU1) = 2/3 * F
99 - capacity(CPU1) = C/3
108 workload on CPU1
109 CPU1 work ^
175 - capacity(CPU1) = C/3
184 CPU1 work ^
337 capacity(CPU1) = C / 3
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| H A D | sched-energy.rst | 152 CPU0 CPU1 CPU2 CPU3
168 * CPU1: 300 / 341 * 150 = 131
177 CPU0 CPU1 CPU2 CPU3
186 * CPU1: 100 / 341 * 150 = 43
195 CPU0 CPU1 CPU2 CPU3
203 * CPU1: 100 / 512 * 300 = 58
212 CPU0 CPU1 CPU2 CPU3
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| /linux/tools/testing/selftests/powerpc/benchmarks/ |
| H A D | context_switch.c | 176 static void pipe_setup(int cpu1, int cpu2) in pipe_setup() argument
219 static void yield_setup(int cpu1, int cpu2) in yield_setup() argument
221 if (cpu1 != cpu2) { in yield_setup()
321 static void futex_setup(int cpu1, int cpu2) in futex_setup() argument
403 fprintf(stderr, "Usage: context_switch2 <options> CPU1 CPU2\n\n"); in usage()
419 int cpu1; in main() local
469 cpu1 = cpu2 = pick_online_cpu(); in main()
471 cpu1 = atoi(argv[optind++]); in main()
491 cpu1, cpu2, touch_fp ? "yes" : "no", touch_altivec ? "yes" : "no", in main()
499 actions->setup(cpu1, cpu2); in main()
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| /linux/Documentation/scheduler/ |
| H A D | sched-capacity.rst | 62 - work_per_hz(CPU1) = W/2
68 - capacity(CPU1) = C/2
70 To draw the parallel with Arm big.LITTLE, CPU0 would be a big while CPU1 would
81 CPU1 work ^
87 work W in T units of time. On the other hand, CPU1 has half the capacity of
97 - max_freq(CPU1) = 2/3 * F
102 - capacity(CPU1) = C/3
112 workload on CPU1
113 CPU1 work ^
191 - capacity(CPU1) = C/3
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| H A D | sched-energy.rst | 152 composed of two CPUs each. CPU0 and CPU1 are little CPUs; CPU2 and CPU3
179 CPU0 CPU1 CPU2 CPU3
186 CPU1 and CPU3. Then it will estimate the energy of the system if P was
192 **Case 1. P is migrated to CPU1**::
198 * CPU1: 300 / 341 * 150 = 131
207 CPU0 CPU1 CPU2 CPU3
216 * CPU1: 100 / 341 * 150 = 43
225 CPU0 CPU1 CPU2 CPU3
234 * CPU1: 100 / 512 * 300 = 58
243 CPU0 CPU1 CPU2 CPU3
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | ulcb-simple-audio-card.dtsi | 10 * (B) CPU1 ----> HDMI
41 * (B) CPU1 -> HDMI
66 * (B) CPU1 -> HDMI
87 * (B) CPU1 -> HDMI
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| H A D | ulcb-audio-graph-card.dtsi | 10 * (B) CPU1 -----> HDMI
24 &snd_ulcb2 /* (B) CPU1 -> HDMI */
46 * (B) CPU1 -> HDMI
79 * (B) CPU1 -> HDMI
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| H A D | ulcb-audio-graph-card-mix+split.dtsi | 13 * (B) CPU1 (2ch) --/ (MIX-1)
31 &snd_ulcb2 /* (B) CPU1 */
52 /* (B) CPU1 -> (X) ak4613 */
83 * (B) CPU1
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| H A D | ulcb-audio-graph-card2-mix+split.dtsi | 13 * (B) CPU1 (2ch) --/ (MIX-1)
30 &fe_b /* (B) CPU1 */
45 * (B) CPU1 (MIX-1)
100 * (B) CPU1
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| /linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-opp-zaius.dts | 322 /* CPU1 PRM 0.7V */
323 /* CPU1 PRM 1.2V CH03 */
324 /* CPU1 PRM 0.8V */
325 /* CPU1 PRM 1.2V CH47 */
431 /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */
432 /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */
433 /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */
434 /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
435 /* CPU1 VR ISL68137 0.8V PMBUS @60h */
464 * CPU1 debug
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| /linux/kernel/sched/ |
| H A D | membarrier.c | 22 * CPU1 after the IPI-induced memory barrier:
24 * CPU0 CPU1
38 * The write to y and load from x by CPU1 are unordered by the hardware,
46 * before the IPI-induced memory barrier on CPU1.
56 * order to enforce the guarantee that any writes occurring on CPU1 before
60 * CPU0 CPU1
80 * after the IPI-induced memory barrier on CPU1.
84 * CPU0 CPU1
102 * and Thread B). Thread A runs on CPU0, Thread B runs on CPU1.
104 * CPU0 CPU1
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| /linux/arch/sparc/include/asm/ |
| H A D | mmu_context_64.h | 111 * set cpu1's bit in cpu_vm_mask in switch_mm()
113 * reset cpu_vm_mask to just cpu1 in switch_mm()
120 * before the TSB grow performed on cpu1. cpu1 did not cross-call in switch_mm()
122 * only had cpu1 set in it. in switch_mm()
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-g12b.dtsi | 23 cpu = <&cpu1>;
56 cpu1: cpu@1 { label
123 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
132 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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| /linux/arch/riscv/include/asm/ |
| H A D | membarrier.h | 34 * - [CPU1] stores to rq->curr (by the scheduler); in membarrier_arch_switch_mm()
38 * CPU1; this means membarrier relies on switch_mm() to in membarrier_arch_switch_mm()
41 * - [CPU1] switch_mm() loads icache_stale_mask; if the bit in membarrier_arch_switch_mm()
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