Searched full:cmus (Results 1 – 5 of 5) sorted by relevance
54962 … (0x3<<4) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 0…54970 … (0x3<<9) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 0…
58220 … (0x3<<4) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 0…58228 … (0x3<<9) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 0…
60365 … (0x3<<4) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 0…60373 … (0x3<<9) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 0…