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/linux/drivers/mailbox/
H A Dmtk-cmdq-mailbox.c19 #include <linux/mailbox/mtk-cmdq-mailbox.h>
77 struct cmdq *cmdq; member
84 struct cmdq { struct
119 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); in cmdq_get_mbox_priv() local
121 priv->shift_pa = cmdq->pdata->shift; in cmdq_get_mbox_priv()
122 priv->mminfra_offset = cmdq->pdata->mminfra_offset; in cmdq_get_mbox_priv()
128 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); in cmdq_get_shift_pa() local
130 return cmdq->pdata->shift; in cmdq_get_shift_pa()
134 static void cmdq_vm_init(struct cmdq *cmdq) in cmdq_vm_init() argument
140 if (!cmdq->pdata->gce_vm) in cmdq_vm_init()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dcmdq.c26 nvkm_falcon_cmdq_has_room(struct nvkm_falcon_cmdq *cmdq, u32 size, bool *rewind) in nvkm_falcon_cmdq_has_room() argument
28 u32 head = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->head_reg); in nvkm_falcon_cmdq_has_room()
29 u32 tail = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->tail_reg); in nvkm_falcon_cmdq_has_room()
35 free = cmdq->offset + cmdq->size - head; in nvkm_falcon_cmdq_has_room()
40 head = cmdq->offset; in nvkm_falcon_cmdq_has_room()
51 nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size) in nvkm_falcon_cmdq_push() argument
53 struct nvkm_falcon *falcon = cmdq->qmgr->falcon; in nvkm_falcon_cmdq_push()
54 nvkm_falcon_pio_wr(falcon, data, 0, 0, DMEM, cmdq->position, size, 0, false); in nvkm_falcon_cmdq_push()
55 cmdq->position += ALIGN(size, QUEUE_ALIGNMENT); in nvkm_falcon_cmdq_push()
59 nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq) in nvkm_falcon_cmdq_rewind() argument
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/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_msgq.c31 static void bfa_msgq_cmdq_dbell(struct bfa_msgq_cmdq *cmdq);
32 static void bfa_msgq_cmdq_copy_rsp(struct bfa_msgq_cmdq *cmdq);
43 bfa_fsm_state_decl(cmdq, stopped, struct bfa_msgq_cmdq, enum cmdq_event);
44 bfa_fsm_state_decl(cmdq, init_wait, struct bfa_msgq_cmdq, enum cmdq_event);
45 bfa_fsm_state_decl(cmdq, ready, struct bfa_msgq_cmdq, enum cmdq_event);
46 bfa_fsm_state_decl(cmdq, dbell_wait, struct bfa_msgq_cmdq,
50 cmdq_sm_stopped_entry(struct bfa_msgq_cmdq *cmdq) in cmdq_sm_stopped_entry() argument
54 cmdq->producer_index = 0; in cmdq_sm_stopped_entry()
55 cmdq->consumer_index = 0; in cmdq_sm_stopped_entry()
56 cmdq->flags = 0; in cmdq_sm_stopped_entry()
[all …]
/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_lib.c25 static int nitrox_cmdq_init(struct nitrox_cmdq *cmdq, int align_bytes) in nitrox_cmdq_init() argument
27 struct nitrox_device *ndev = cmdq->ndev; in nitrox_cmdq_init()
29 cmdq->qsize = (ndev->qlen * cmdq->instr_size) + align_bytes; in nitrox_cmdq_init()
30 cmdq->unalign_base = dma_alloc_coherent(DEV(ndev), cmdq->qsize, in nitrox_cmdq_init()
31 &cmdq->unalign_dma, in nitrox_cmdq_init()
33 if (!cmdq->unalign_base) in nitrox_cmdq_init()
36 cmdq->dma = PTR_ALIGN(cmdq->unalign_dma, align_bytes); in nitrox_cmdq_init()
37 cmdq->base = cmdq->unalign_base + (cmdq->dma - cmdq->unalign_dma); in nitrox_cmdq_init()
38 cmdq->write_idx = 0; in nitrox_cmdq_init()
40 spin_lock_init(&cmdq->cmd_qlock); in nitrox_cmdq_init()
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H A Dnitrox_reqmgr.c230 struct nitrox_cmdq *cmdq) in backlog_list_add() argument
234 spin_lock_bh(&cmdq->backlog_qlock); in backlog_list_add()
235 list_add_tail(&sr->backlog, &cmdq->backlog_head); in backlog_list_add()
236 atomic_inc(&cmdq->backlog_count); in backlog_list_add()
238 spin_unlock_bh(&cmdq->backlog_qlock); in backlog_list_add()
242 struct nitrox_cmdq *cmdq) in response_list_add() argument
246 spin_lock_bh(&cmdq->resp_qlock); in response_list_add()
247 list_add_tail(&sr->response, &cmdq->response_head); in response_list_add()
248 spin_unlock_bh(&cmdq->resp_qlock); in response_list_add()
252 struct nitrox_cmdq *cmdq) in response_list_del() argument
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/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_cmdq.c78 #define cmdq_to_cmdqs(cmdq) container_of((cmdq) - (cmdq)->cmdq_type, \ argument
79 struct hinic_cmdqs, cmdq[0])
320 static void cmdq_set_db(struct hinic_cmdq *cmdq, in cmdq_set_db() argument
332 writel(db_info, CMDQ_DB_ADDR(cmdq->db_base, prod_idx)); in cmdq_set_db()
335 static int cmdq_sync_cmd_direct_resp(struct hinic_cmdq *cmdq, in cmdq_sync_cmd_direct_resp() argument
343 struct hinic_wq *wq = cmdq->wq; in cmdq_sync_cmd_direct_resp()
348 spin_lock_bh(&cmdq->cmdq_lock); in cmdq_sync_cmd_direct_resp()
353 spin_unlock_bh(&cmdq->cmdq_lock); in cmdq_sync_cmd_direct_resp()
359 wrapped = cmdq->wrapped; in cmdq_sync_cmd_direct_resp()
364 cmdq->wrapped = !cmdq->wrapped; in cmdq_sync_cmd_direct_resp()
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H A Dhinic_hw_io.c119 dev_err(&pdev->dev, "Failed to allocate cmdq buf\n"); in write_sq_ctxts()
163 dev_err(&pdev->dev, "Failed to allocate cmdq buf\n"); in write_rq_ctxts()
220 dev_err(&pdev->dev, "Failed to allocate cmdq buf\n"); in hinic_clean_queue_offload_ctxt()
533 enum hinic_cmdq_type cmdq, type; in hinic_io_init() local
565 for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) { in hinic_io_init()
568 dev_err(&pdev->dev, "Failed to get cmdq db area\n"); in hinic_io_init()
573 func_to_io->cmdq_db_area[cmdq] = db_area; in hinic_io_init()
600 for (type = HINIC_CMDQ_SYNC; type < cmdq; type++) in hinic_io_init()
619 enum hinic_cmdq_type cmdq; in hinic_io_free() local
628 for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) in hinic_io_free()
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H A Dhinic_hw_wq.c162 * cmdq_allocate_page - allocate page for cmdq
163 * @cmdq_pages: the pages of the cmdq queue struct to hold the page
176 * cmdq_free_page - free page from cmdq
177 * @cmdq_pages: the pages of the cmdq queue struct that hold the page
588 * @cmdq_pages: will hold the pages of the cmdq
591 * @cmdq_blocks: number of cmdq blocks/wq to allocate
638 dev_err(&pdev->dev, "Failed to allocate CMDQ page\n"); in hinic_wqs_cmdq_alloc()
662 dev_err(&pdev->dev, "Failed to alloc CMDQ blocks\n"); in hinic_wqs_cmdq_alloc()
684 * @cmdq_pages: hold the pages of the cmdq
/linux/drivers/infiniband/hw/bng_re/
H A Dbng_fw.c56 bng_re_free_hwq(rcfw->res, &rcfw->cmdq.hwq); in bng_re_free_rcfw_channel()
66 struct bng_re_cmdq_ctx *cmdq; in bng_re_alloc_fw_channel() local
70 cmdq = &rcfw->cmdq; in bng_re_alloc_fw_channel()
95 if (bng_re_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) { in bng_re_alloc_fw_channel()
97 "HW channel CMDQ allocation failed\n"); in bng_re_alloc_fw_channel()
101 rcfw->crsqe_tbl = kzalloc_objs(*rcfw->crsqe_tbl, cmdq->hwq.max_elements); in bng_re_alloc_fw_channel()
119 struct bng_re_hwq *hwq = &rcfw->cmdq.hwq; in bng_re_process_qp_event()
135 * cmdq->lock needs to be acquired to synchronie in bng_re_process_qp_event()
148 &rcfw->cmdq in bng_re_process_qp_event()
277 struct bng_re_cmdq_ctx *cmdq; __send_message_basic_sanity() local
307 struct bng_re_cmdq_ctx *cmdq; __send_message() local
403 struct bng_re_cmdq_ctx *cmdq; __wait_for_resp() local
631 struct bng_re_cmdq_ctx *cmdq; bng_re_disable_rcfw_channel() local
648 struct bng_re_cmdq_ctx *cmdq; bng_re_start_rcfw() local
674 struct bng_re_cmdq_ctx *cmdq; bng_re_enable_fw_channel() local
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/linux/drivers/infiniband/hw/bnxt_re/
H A Dqplib_rcfw.c114 struct bnxt_qplib_cmdq_ctx *cmdq; in bnxt_re_is_fw_stalled() local
118 cmdq = &rcfw->cmdq; in bnxt_re_is_fw_stalled()
120 if (time_after(jiffies, cmdq->last_seen + in bnxt_re_is_fw_stalled()
123 "%s: FW STALL Detected. cmdq[%#x]=%#x waited (%d > %d) msec active %d ", in bnxt_re_is_fw_stalled()
125 jiffies_to_msecs(jiffies - cmdq->last_seen), in bnxt_re_is_fw_stalled()
147 struct bnxt_qplib_cmdq_ctx *cmdq; in __wait_for_resp() local
151 cmdq = &rcfw->cmdq; in __wait_for_resp()
155 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags)) in __wait_for_resp()
157 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags)) in __wait_for_resp()
160 wait_event_timeout(cmdq->waitq, in __wait_for_resp()
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/linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.c492 /* If CMDQ ring is full, SW HEAD and HW HEAD may be different, in hclge_comm_cmd_send()
541 struct hclge_comm_cmq *cmdq = &hw->cmq; in hclge_comm_cmd_uninit() local
550 spin_lock_bh(&cmdq->csq.lock); in hclge_comm_cmd_uninit()
551 spin_lock(&cmdq->crq.lock); in hclge_comm_cmd_uninit()
553 spin_unlock(&cmdq->crq.lock); in hclge_comm_cmd_uninit()
554 spin_unlock_bh(&cmdq->csq.lock); in hclge_comm_cmd_uninit()
556 hclge_comm_free_cmd_desc(&cmdq->csq); in hclge_comm_cmd_uninit()
557 hclge_comm_free_cmd_desc(&cmdq->crq); in hclge_comm_cmd_uninit()
563 struct hclge_comm_cmq *cmdq = &hw->cmq; in hclge_comm_cmd_queue_init() local
567 spin_lock_init(&cmdq->csq.lock); in hclge_comm_cmd_queue_init()
[all …]
/linux/drivers/gpu/nova-core/
H A Dgsp.rs22 pub(crate) mod cmdq;
34 gsp::cmdq::Cmdq,
127 pub(crate) cmdq: Cmdq,
146 cmdq <- Cmdq::new(dev), in new()
147 rmargs: Coherent::init(dev, GFP_KERNEL, GspArgumentsPadded::new(&cmdq))?, in new()
21 pub(crate) mod cmdq; global() module
125 pub(crate) cmdq: Cmdq, global() field
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dbase.c45 struct nvkm_falcon_cmdq *cmdq = sec2->cmdq; in nvkm_sec2_fini() local
56 ret = nvkm_falcon_cmdq_send(cmdq, &cmd, nvkm_sec2_finimsg, sec2, in nvkm_sec2_fini()
68 nvkm_falcon_cmdq_fini(cmdq); in nvkm_sec2_fini()
119 nvkm_falcon_cmdq_del(&sec2->cmdq); in nvkm_sec2_dtor()
159 (ret = nvkm_falcon_cmdq_new(sec2->qmgr, "cmdq", &sec2->cmdq)) || in nvkm_sec2_new_()
H A Dga102.c50 nvkm_falcon_cmdq_init(sec2->cmdq, msg.queue_info[i].index, in ga102_sec2_initmsg()
104 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in ga102_sec2_acr_bootstrap_falcon()
137 .cmdq = { 0xc00, 0xc04, 8 },
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Drpc.c80 * GSP consumes the elements from the cmdq and always writes the result
369 msg->sequence = gsp->cmdq.seq++; in r535_gsp_cmdq_push()
377 wptr = *gsp->cmdq.wptr; in r535_gsp_cmdq_push()
380 free = *gsp->cmdq.rptr + gsp->cmdq.cnt - wptr - 1; in r535_gsp_cmdq_push()
381 if (free >= gsp->cmdq.cnt) in r535_gsp_cmdq_push()
382 free -= gsp->cmdq.cnt; in r535_gsp_cmdq_push()
394 cqe = (void *)((u8 *)gsp->shm.cmdq.ptr + 0x1000 + wptr * 0x1000); in r535_gsp_cmdq_push()
395 step = min_t(u32, free, (gsp->cmdq.cnt - wptr)); in r535_gsp_cmdq_push()
401 if (wptr == gsp->cmdq.cnt) in r535_gsp_cmdq_push()
408 nvkm_trace(&gsp->subdev, "cmdq: wptr %d\n", wptr); in r535_gsp_cmdq_push()
[all …]
H A Dgsp.c53 mutex_lock(&gsp->cmdq.mutex); in r535_gsp_msgq_work()
56 mutex_unlock(&gsp->cmdq.mutex); in r535_gsp_msgq_work()
1140 } *cmdq, *msgq; in r535_gsp_shared_init() local
1143 gsp->shm.cmdq.size = 0x40000; in r535_gsp_shared_init()
1146 gsp->shm.ptes.nr = (gsp->shm.cmdq.size + gsp->shm.msgq.size) >> GSP_PAGE_SHIFT; in r535_gsp_shared_init()
1151 gsp->shm.cmdq.size + in r535_gsp_shared_init()
1158 gsp->shm.cmdq.ptr = (u8 *)gsp->shm.ptes.ptr + gsp->shm.ptes.size; in r535_gsp_shared_init()
1159 gsp->shm.msgq.ptr = (u8 *)gsp->shm.cmdq.ptr + gsp->shm.cmdq.size; in r535_gsp_shared_init()
1164 cmdq = gsp->shm.cmdq.ptr; in r535_gsp_shared_init()
1165 cmdq->tx.version = 0; in r535_gsp_shared_init()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dsge.c168 struct cmdQ { struct
182 spinlock_t lock; /* Lock to protect cmdQ enqueuing */ argument
208 /* Bit flags for cmdQ.status */
265 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; member
474 struct cmdQ *q = &sge->cmdQ[0]; in sched_skb()
612 static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n) in free_cmdQ_buffers()
653 struct cmdQ *q = &sge->cmdQ[i]; in free_tx_resources()
677 struct cmdQ *q = &sge->cmdQ[i]; in alloc_tx_resources()
706 sge->cmdQ[0].stop_thres = sge->adapter->params.nports * in alloc_tx_resources()
750 setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size, in configure_sge()
[all …]
/linux/drivers/gpu/nova-core/gsp/
H A Dfw.rs38 cmdq::Cmdq, //
60 use crate::gsp::cmdq::{
877 /// Creates the arguments for starting the GSP up using `cmdq` as its command queue.
878 pub(crate) fn new(cmdq: &Cmdq) -> impl Init<Self> + '_ {
881 messageQueueInitArguments <- MessageQueueInitArguments::new(cmdq),
906 pub(crate) fn new(cmdq: &Cmdq) -> impl Init<Self> + '_ {
908 inner <- GspArgumentsCached::new(cmdq),
[all...]
H A Dboot.rs29 cmdq::Cmdq,
146 self.cmdq in boot()
148 self.cmdq in boot()
154 commands::wait_gsp_init_done(&self.cmdq)?; in boot()
157 let info = self.cmdq.send_command(bar, commands::GetGspStaticInfo)?; in boot()
168 cmdq: &Cmdq, in boot()
174 cmdq.send_command(bar, commands::UnloadingGuestDriver::new(mode))?; in boot()
200 &self.cmdq, in boot()
[all...]
/linux/include/dt-bindings/gce/
H A Dmt8186-gce.h82 /* CMDQ: debug */
85 /* CMDQ: P7: debug */
348 /* CMDQ sw tokens
367 /* Notify normal CMDQ there are some secure task done
372 /* CMDQ use sw token */
419 /* CMDQ sw tokens END */
/linux/Documentation/devicetree/bindings/mailbox/
H A Dmediatek,gce-props.yaml15 (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
19 driver. A device driver that uses the CMDQ driver to configure its hardware
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_padding.c12 #include <linux/soc/mediatek/mtk-cmdq.h>
30 * @cmdq_reg: CMDQ setting of the Padding
33 * CMDQ settings, we stored these differences all together.
/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_trace.h175 DECLARE_EVENT_CLASS(cmdq,
195 TP_printk("%s cmdq opcode:0x%x, flag:0x%x, retval:0x%x, data:%s\n",
201 DEFINE_EVENT(cmdq, hns_cmdq_req,
205 DEFINE_EVENT(cmdq, hns_cmdq_resp,
/linux/include/linux/soc/mediatek/
H A Dmtk-mmsys.h10 #include <linux/mailbox/mtk-cmdq-mailbox.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8196-gce.h34 * The CMDQ driver can use the following event ID definitions to allow
35 * the client driver to use wait and clear APIs provided by CMDQ, enabling
246 * The CMDQ driver can use the following event ID definitions to allow
247 * the client driver to use wait and clear APIs provided by CMDQ, enabling
578 * Notify normal CMDQ there are some secure task done
582 /* CMDQ use software token */

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