Home
last modified time | relevance | path

Searched full:clr (Results 1 – 25 of 283) sorted by relevance

12345678910>>...12

/linux/drivers/net/ethernet/intel/e1000e/
H A Dregs.h32 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
121 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
122 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
123 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
124 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
125 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
126 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
127 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
128 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
129 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h21 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
30 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
187 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
188 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
189 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
190 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
191 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
192 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
193 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
194 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/linux/include/trace/events/
H A Dthp.h41 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set),
42 TP_ARGS(addr, pte, clr, set),
46 __field(unsigned long, clr)
53 __entry->clr = clr;
58 …page update at addr 0x%lx and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, …
62 TP_PROTO(unsigned long addr, unsigned long pmd, unsigned long clr, unsigned long set),
63 TP_ARGS(addr, pmd, clr, set)
67 TP_PROTO(unsigned long addr, unsigned long pud, unsigned long clr, unsigned long set),
68 TP_ARGS(addr, pud, clr, set)
/linux/arch/m68k/math-emu/
H A Dfp_util.S70 2: clr.l %d0
99 clr.l %d1 | sign defaults to zero
109 clr.l (%a0)
116 clr.l (%a0)+
117 clr.l (%a0)+
118 clr.l (%a0)
142 clr.l (%a0) | low lword = 0
236 clr.b (%a0)
274 clr.l %d0
279 clr.w -(%a0)
[all …]
/linux/arch/m68k/ifpsp060/src/
H A Ditest.S81 clr.l TESTCTR(%a6)
91 clr.l TESTCTR(%a6)
101 clr.l TESTCTR(%a6)
111 clr.l TESTCTR(%a6)
121 clr.l TESTCTR(%a6)
132 clr.l TESTCTR(%a6)
142 clr.l TESTCTR(%a6)
169 clr.l %d1
181 clr.l IREGS+0x8(%a6)
182 clr.l IREGS+0xc(%a6)
[all …]
H A Dftest.S98 clr.l TESTCTR(%a6)
108 clr.l TESTCTR(%a6)
118 clr.l TESTCTR(%a6)
126 clr.l TESTCTR(%a6)
150 clr.l TESTCTR(%a6)
176 clr.l TESTCTR(%a6)
184 clr.l TESTCTR(%a6)
192 clr.l TESTCTR(%a6)
200 clr.l TESTCTR(%a6)
208 clr.l TESTCTR(%a6)
[all …]
H A Dilsp.S298 clr.l %d1
313 clr.w %d5
327 clr.l DDNORMAL(%a6) # count of shifts for normalization
328 clr.b DDSECOND(%a6) # clear flag for quotient digits
329 clr.l %d1 # %d1 will hold trial quotient
362 clr.w %d6 # word u3 left
405 clr.l %d2
408 clr.w %d3 # %d3 now ls word of divisor
412 clr.w %d3 # %d3 now ms word of divisor
421 clr.l %d1
[all …]
/linux/drivers/video/fbdev/
H A Datafb_utils.h85 " lsr.l #1,%1 ; jcc 1f ; clr.b (%0)+\n" in fb_memclear()
86 "1: lsr.l #1,%1 ; jcc 1f ; clr.w (%0)+\n" in fb_memclear()
87 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+\n" in fb_memclear()
88 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
96 " lsr.l #1,%2 ; jcc 1f ; clr.b (%0)+ ; subq.w #1,%1\n" in fb_memclear()
98 " clr.w (%0)+ ; subq.w #2,%1 ; jra 2f\n" in fb_memclear()
100 " clr.w (%0)+ ; subq.w #2,%1\n" in fb_memclear()
102 " lsr.l #1,%1 ; jcc 3f ; clr.l (%0)+\n" in fb_memclear()
103 "3: lsr.l #1,%1 ; jcc 4f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
105 "5: clr.l (%0)+; clr.l (%0)+ ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
[all …]
/linux/arch/sparc/lib/
H A Dffs.S14 clr %o0
21 clr %o1 /* 2 */
25 1: clr %o2
31 clr %o3
34 clr %o4
40 clr %o5
/linux/Documentation/admin-guide/
H A Dmono.rst5 (in the form of .exe files) without the need to use the mono CLR
11 1) You MUST FIRST install the Mono CLR support, either by downloading
21 Once the Mono CLR support has been installed, just check that
50 # Register support for .NET CLR binaries
53 # the Mono CLR runtime (usually /usr/local/bin/mono
55 echo ':CLR:M::MZ::/usr/bin/mono:' > /proc/sys/fs/binfmt_misc/register
/linux/arch/m68k/ifpsp060/
H A Dos.S94 clr.l %d1 | return success
101 clr.l %d1 | return success
127 clr.l %d1 | return success
134 clr.l %d1 | return success
151 clr.l %d0 | clear whole longword
152 clr.l %d1 | assume success
187 clr.l %d1 | assume success
188 clr.l %d0 | clear whole longword
223 clr.l %d1 | assume success
245 clr.l %d1 | assume success
[all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-8xx.h123 unsigned long clr, unsigned long set, int huge);
135 unsigned long clr = ~pte_val(entry) & _PAGE_RO; in __ptep_set_access_flags() local
138 pte_update(vma->vm_mm, address, ptep, clr, set, huge); in __ptep_set_access_flags()
188 unsigned long clr, unsigned long set, int huge) in __pte_update() argument
192 pte_basic_t new = (old & ~(pte_basic_t)clr) | set; in __pte_update()
211 unsigned long clr, unsigned long set, int huge) in pte_update() argument
218 old = __pte_update(mm, addr, pte_offset_kernel(pmdp, 0), clr, set, huge); in pte_update()
219 __pte_update(mm, addr, pte_offset_kernel(pmdp + 1, 0), clr, set, huge); in pte_update()
221 old = __pte_update(mm, addr, ptep, clr, set, huge); in pte_update()
/linux/drivers/clocksource/
H A Dtimer-armada-370-xp.c88 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
173 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local
178 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu()
179 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu()
245 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
264 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
267 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
268 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
/linux/arch/arm/mach-rpc/
H A Dirq.c14 #define CLR 0x04 macro
132 writeb(mask, base + CLR); in iomd_irq_mask_ack()
168 unsigned int irq, clr, set; in rpc_init_irq() local
181 clr = IRQ_NOREQUEST; in rpc_init_irq()
185 clr |= IRQ_NOPROBE; in rpc_init_irq()
195 irq_modify_status(irq, clr, set); in rpc_init_irq()
203 irq_modify_status(irq, clr, set); in rpc_init_irq()
211 irq_modify_status(irq, clr, set); in rpc_init_irq()
218 irq_modify_status(irq, clr, set); in rpc_init_irq()
/linux/arch/powerpc/include/asm/
H A Ddcr-native.h112 unsigned clr, unsigned set) in __dcri_clrset() argument
120 val = (mfdcrx(base_data) & ~clr) | set; in __dcri_clrset()
124 val = (__mfdcr(base_data) & ~clr) | set; in __dcri_clrset()
138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ argument
140 reg, clr, set)
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h135 /* [31:16] RW intr_stat/clr. Default 0.
139 * [ 21] stat/clr of eof interrupt
141 * [ 19] stat/clr of de_rise interrupt
142 * [ 18] stat/clr of vs_fall interrupt
143 * [ 17] stat/clr of vs_rise interrupt
144 * [ 16] stat/clr of dwc_edpite interrupt
/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h773 * R/clr - register is read only and is cleared when read
799 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
914 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
915 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
916 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
917 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
918 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
919 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
920 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
921 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c127 u32 set, clr; in ath9k_hw_wow_apply_pattern() local
160 clr = AR_WOW_LENGTH1_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
165 clr = AR_WOW_LENGTH2_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
170 clr = AR_WOW_LENGTH3_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern()
175 clr = AR_WOW_LENGTH4_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
/linux/kernel/irq/
H A Ddevres.c283 unsigned int clr; member
291 irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); in devm_irq_remove_generic_chip()
302 * @clr: IRQ_* bits to clear
311 unsigned int clr, unsigned int set) in devm_irq_setup_generic_chip() argument
320 irq_setup_generic_chip(gc, msk, flags, clr, set); in devm_irq_setup_generic_chip()
324 dr->clr = clr; in devm_irq_setup_generic_chip()
H A Dgeneric-chip.c175 * irq_gc_set_wake - Set/clr wake bit for an interrupt
381 * @clr: IRQ_* bits to clear in the mapping function
388 unsigned int clr, unsigned int set, in __irq_alloc_domain_generic_chips() argument
396 .irq_flags_to_clear = clr, in __irq_alloc_domain_generic_chips()
523 * @clr: IRQ_* bits to clear
531 enum irq_gc_flags flags, unsigned int clr, in irq_setup_generic_chip() argument
561 irq_modify_status(i, clr, set); in irq_setup_generic_chip()
595 * @clr: IRQ_* bits to clear
601 unsigned int clr, unsigned int set) in irq_remove_generic_chip() argument
629 irq_modify_status(virq, clr, set); in irq_remove_generic_chip()
/linux/arch/sparc/include/asm/
H A Duaccess_64.h97 "clr %0\n" \
129 "clr %0\n" \
170 "clr %0\n" \
176 "clr %1\n\t" \
208 "clr %0\n" \
214 "clr %1\n\t" \
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-gpio-defs.h296 uint64_t clr:24; member
298 uint64_t clr:24;
305 uint64_t clr:16; member
307 uint64_t clr:16;
314 uint64_t clr:20; member
316 uint64_t clr:20;
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dwndw.c136 union nv50_wndw_atom_mask clr = { in nv50_wndw_flush_clr() local
137 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), in nv50_wndw_flush_clr()
139 if (clr.sema ) wndw->func-> sema_clr(wndw); in nv50_wndw_flush_clr()
140 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); in nv50_wndw_flush_clr()
141 if (clr.xlut ) wndw->func-> xlut_clr(wndw); in nv50_wndw_flush_clr()
142 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
143 if (clr.image) wndw->func->image_clr(wndw); in nv50_wndw_flush_clr()
419 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check_lut()
434 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
510 asyw->clr.ntfy = armw->ntfy.handle != 0; in nv50_wndw_atomic_check()
[all …]
/linux/drivers/gpio/
H A Dgpio-mmio.c512 * - set/clear pair (named "set" and "clr").
517 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
538 if (cfg->set && cfg->clr) { in gpio_mmio_setup_io()
540 chip->reg_clr = cfg->clr; in gpio_mmio_setup_io()
543 } else if (cfg->set && !cfg->clr) { in gpio_mmio_setup_io()
739 void __iomem *clr; in gpio_mmio_pdev_probe() local
762 clr = gpio_mmio_map(pdev, "clr", sz); in gpio_mmio_pdev_probe()
763 if (IS_ERR(clr)) in gpio_mmio_pdev_probe()
764 return PTR_ERR(clr); in gpio_mmio_pdev_probe()
789 .clr = clr, in gpio_mmio_pdev_probe()
/linux/drivers/iio/humidity/
H A Dhdc3020.c492 int s_val, thresh, clr, ret; in hdc3020_write_thresh() local
517 clr = ret; in hdc3020_write_thresh()
534 s_clr = (s64)hdc3020_thresh_get_temp(clr) * 1000000; in hdc3020_write_thresh()
560 reg_val = hdc3020_thresh_set_temp(s_clr, clr); in hdc3020_write_thresh()
578 s_clr = (s64)hdc3020_thresh_get_hum(clr) * 1000000; in hdc3020_write_thresh()
603 reg_val = hdc3020_thresh_set_hum(s_clr, clr); in hdc3020_write_thresh()
625 int thresh, clr, ret; in hdc3020_read_thresh() local
653 clr = hdc3020_thresh_get_temp(ret); in hdc3020_read_thresh()
654 *val = abs(thresh - clr) * MILLI; in hdc3020_read_thresh()
672 clr = hdc3020_thresh_get_hum(ret); in hdc3020_read_thresh()
[all …]

12345678910>>...12