| /linux/Documentation/devicetree/bindings/media/ |
| H A D | mediatek,vcodec-subdev-decoder.yaml | 231 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
237 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
257 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
263 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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| H A D | mediatek,vcodec-decoder.yaml | 177 <&topckgen CLK_TOP_VDEC_SEL>,
192 <&topckgen CLK_TOP_VDEC_SEL>,
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| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6735-topckgen.h | 54 #define CLK_TOP_VDEC_SEL 46 macro
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| H A D | mt8135-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mediatek,mt6795-clk.h | 95 #define CLK_TOP_VDEC_SEL 84 macro
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| H A D | mt8173-clk.h | 97 #define CLK_TOP_VDEC_SEL 87 macro
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| H A D | mt2712-clk.h | 134 #define CLK_TOP_VDEC_SEL 103 macro
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| H A D | mt2701-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt8192-clk.h | 64 #define CLK_TOP_VDEC_SEL 52 macro
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8192.dtsi | 637 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1719 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1725 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1745 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1751 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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| H A D | mt8173.dtsi | 1410 <&topckgen CLK_TOP_VDEC_SEL>,
1425 <&topckgen CLK_TOP_VDEC_SEL>,
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| H A D | mt2712e.dtsi | 290 <&topckgen CLK_TOP_VDEC_SEL>;
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6735-topckgen.c | 340 …MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK…
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| H A D | clk-mt8135.c | 382 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
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| H A D | clk-mt6795-topckgen.c | 461 TOP_MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x50, 8, 4, 15, 0),
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| H A D | clk-mt8173-topckgen.c | 540 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
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| H A D | clk-mt2701.c | 498 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
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| H A D | clk-mt2712.c | 651 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15),
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| H A D | clk-mt8192.c | 669 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
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