Home
last modified time | relevance | path

Searched full:clk_top_spislv_sel (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-slave-mt27xx.yaml56 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
/linux/include/dt-bindings/clock/
H A Dmt2712-clk.h188 #define CLK_TOP_SPISLV_SEL 157 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c736 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", spislv_parents, 0x540, 24, 3, 31),
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;