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Searched full:clk_top_mm_sel (Results 1 – 18 of 18) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h52 #define CLK_TOP_MM_SEL 44 macro
H A Dmediatek,mt6795-clk.h93 #define CLK_TOP_MM_SEL 82 macro
H A Dmt8173-clk.h95 #define CLK_TOP_MM_SEL 85 macro
H A Dmt6765-clk.h133 #define CLK_TOP_MM_SEL 98 macro
H A Dmediatek,mt8365-clk.h73 #define CLK_TOP_MM_SEL 63 macro
H A Dmt2712-clk.h132 #define CLK_TOP_MM_SEL 101 macro
H A Dmt2701-clk.h87 #define CLK_TOP_MM_SEL 76 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi467 clocks = <&topckgen CLK_TOP_MM_SEL>;
473 clocks = <&topckgen CLK_TOP_MM_SEL>,
480 clocks = <&topckgen CLK_TOP_MM_SEL>;
486 clocks = <&topckgen CLK_TOP_MM_SEL>;
493 clocks = <&topckgen CLK_TOP_MM_SEL>,
1009 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
H A Dmt2712e.dtsi285 clocks = <&topckgen CLK_TOP_MM_SEL>,
H A Dmt8365.dtsi332 clocks = <&topckgen CLK_TOP_MM_SEL>,
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c338 …MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0…
H A Dclk-mt6795-topckgen.c458 TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x40, 24, 3, 31, 0),
H A Dclk-mt8173-topckgen.c537 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
H A Dclk-mt8365.c415 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
H A Dclk-mt6765.c376 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
H A Dclk-mt2701.c493 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
H A Dclk-mt2712.c648 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31),
/linux/arch/arm/boot/dts/mediatek/
H A Dmt2701.dtsi156 clocks = <&topckgen CLK_TOP_MM_SEL>,