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Searched full:clk_top_ethif_sel (Results 1 – 5 of 5) sorted by relevance

/linux/arch/arm/boot/dts/mediatek/
H A Dmt2701.dtsi158 <&topckgen CLK_TOP_ETHIF_SEL>;
613 <&topckgen CLK_TOP_ETHIF_SEL>;
653 <&topckgen CLK_TOP_ETHIF_SEL>;
733 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
H A Dmt7623a.dtsi133 clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
H A Dmt7623.dtsi279 <&topckgen CLK_TOP_ETHIF_SEL>;
768 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
865 <&topckgen CLK_TOP_ETHIF_SEL>;
906 <&topckgen CLK_TOP_ETHIF_SEL>;
966 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
/linux/include/dt-bindings/clock/
H A Dmt2701-clk.h121 #define CLK_TOP_ETHIF_SEL 110 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt2701.c568 MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,