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Searched full:clk_top_ether_50m_rmii_sel (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/net/
H A Dmediatek-dwmac.yaml170 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
173 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
/linux/include/dt-bindings/clock/
H A Dmt2712-clk.h189 #define CLK_TOP_ETHER_50M_RMII_SEL 158 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi745 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
748 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c738 MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", ether_parents, 0x550, 0, 2, 7),