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Searched full:clk_top_aud_mux1_sel (Results 1 – 4 of 4) sorted by relevance

/linux/arch/arm/boot/dts/mediatek/
H A Dmt2701.dtsi435 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
504 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
H A Dmt7623.dtsi636 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
705 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
/linux/include/dt-bindings/clock/
H A Dmt2701-clk.h131 #define CLK_TOP_AUD_MUX1_SEL 120 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt2701.c590 MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,