Searched full:clk_top_apll1_div0 (Results 1 – 6 of 6) sorted by relevance
| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | mediatek,mt8173-afe-pcm.yaml | 80 <&topckgen CLK_TOP_APLL1_DIV0>,
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| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 126 #define CLK_TOP_APLL1_DIV0 115 macro
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| H A D | mt8173-clk.h | 131 #define CLK_TOP_APLL1_DIV0 121 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 511 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
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| H A D | clk-mt8173-topckgen.c | 606 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8173.dtsi | 877 <&topckgen CLK_TOP_APLL1_DIV0>,
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