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/linux/Documentation/devicetree/bindings/sound/
H A Dmt8186-afe-pcm.yaml142 <&topckgen 132>, //CLK_TOP_APLL12_CK_DIV1
H A Dmediatek,mt8188-afe.yaml197 <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
/linux/include/dt-bindings/clock/
H A Dmt8516-clk.h197 #define CLK_TOP_APLL12_CK_DIV1 165 macro
H A Dmediatek,mt8365-clk.h123 #define CLK_TOP_APLL12_CK_DIV1 113 macro
H A Dmt8186-clk.h151 #define CLK_TOP_APLL12_CK_DIV1 132 macro
H A Dmediatek,mt8188-clk.h191 #define CLK_TOP_APLL12_CK_DIV1 180 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8516.c481 DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
H A Dclk-mt8186-topckgen.c674 DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "apll_i2s1_mck_sel",
H A Dclk-mt8167.c670 DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
H A Dclk-mt8365.c555 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel",
H A Dclk-mt8188-topckgen.c1186 DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "top_i2si2", 0x0320, 1, 0x0328, 8, 8),
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186.dtsi1524 <&topckgen CLK_TOP_APLL12_CK_DIV1>,
H A Dmt8188.dtsi1400 <&topckgen CLK_TOP_APLL12_CK_DIV1>,