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Searched full:clk_top_apll1 (Results 1 – 22 of 22) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt8516-clk.h65 #define CLK_TOP_APLL1 33 macro
H A Dmediatek,mt6795-clk.h36 #define CLK_TOP_APLL1 25 macro
H A Dmt8173-clk.h35 #define CLK_TOP_APLL1 25 macro
H A Dmt6765-clk.h76 #define CLK_TOP_APLL1 41 macro
H A Dmediatek,mt8365-clk.h54 #define CLK_TOP_APLL1 44 macro
H A Dmt2712-clk.h74 #define CLK_TOP_APLL1 43 macro
H A Dmt8192-clk.h113 #define CLK_TOP_APLL1 101 macro
H A Dmediatek,mt8188-clk.h83 #define CLK_TOP_APLL1 72 macro
H A Dmt8195-clk.h104 #define CLK_TOP_APLL1 92 macro
/linux/Documentation/devicetree/bindings/sound/
H A Dmt8195-afe-pcm.yaml161 <&topckgen 163>, //CLK_TOP_APLL1
/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c386 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
H A Dclk-mt8173-topckgen.c461 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
H A Dclk-mt8516.c60 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
H A Dclk-mt8167.c67 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
H A Dclk-mt8365.c76 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
H A Dclk-mt6765.c126 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
H A Dclk-mt2712.c82 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
H A Dclk-mt8192.c59 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
H A Dclk-mt8188-topckgen.c1134 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
H A Dclk-mt8195-topckgen.c1100 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi888 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
H A Dmt8192.dtsi1011 <&topckgen CLK_TOP_APLL1>,