Searched full:clk_mm_disp_pwm0mm (Results 1 – 7 of 7) sorted by relevance
| /linux/Documentation/devicetree/bindings/pwm/ |
| H A D | mediatek,pwm-disp.yaml | 78 <&mmsys CLK_MM_DISP_PWM0MM>;
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-mm.c | 67 GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
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| H A D | clk-mt8173-mm.c | 69 GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
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| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 251 #define CLK_MM_DISP_PWM0MM 32 macro
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| H A D | mt8173-clk.h | 279 #define CLK_MM_DISP_PWM0MM 32 macro
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt6795.dtsi | 912 clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>;
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| H A D | mt8173.dtsi | 1263 <&mmsys CLK_MM_DISP_PWM0MM>;
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