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Searched full:clk_fin_pll (Results 1 – 20 of 20) sorted by relevance

/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml167 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
208 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
/linux/include/dt-bindings/clock/
H A Dexynos5410.h13 #define CLK_FIN_PLL 1 macro
H A Dexynos5250.h13 #define CLK_FIN_PLL 1 macro
H A Dexynos5420.h13 #define CLK_FIN_PLL 1 macro
H A Dexynos4.h15 #define CLK_FIN_PLL 3 macro
H A Dexynos3250.h26 #define CLK_FIN_PLL 2 macro
/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi352 clocks = <&cmu CLK_FIN_PLL>;
402 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
403 <&cmu CLK_FIN_PLL>;
455 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
H A Dexynos5250.dtsi237 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
247 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
292 clocks = <&clock CLK_FIN_PLL>;
667 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
698 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
H A Dexynos5420.dtsi295 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
927 clocks = <&clock CLK_FIN_PLL>;
1291 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
H A Dexynos4210.dtsi286 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
H A Dexynos5250-snow-common.dtsi672 assigned-clock-parents = <&clock CLK_FIN_PLL>;
H A Dexynos4x12.dtsi299 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
H A Dexynos5420-peach-pit.dts946 assigned-clock-parents = <&clock CLK_FIN_PLL>;
H A Dexynos5800-peach-pi.dts928 assigned-clock-parents = <&clock CLK_FIN_PLL>;
H A Dexynos4.dtsi70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml199 clocks = <&clock CLK_FIN_PLL>;
/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c228 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
813 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5250_clk_init()
H A Dclk-exynos4.c1059 fclk.id = CLK_FIN_PLL; in exynos4_clk_register_finpll()
1298 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
1312 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
H A Dclk-exynos5420.c448 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
1600 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5x_clk_init()
H A Dclk-exynos3250.c239 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),