Searched full:clk_dram_csi0 (Results 1 – 6 of 6) sorted by relevance
113 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
158 #define CLK_DRAM_CSI0 134 macro
164 #define CLK_DRAM_CSI0 131 macro
182 CCU_GATE(CLK_DRAM_CSI0, "dram-csi0", "pll_ddr", 0x100, 1)
324 <&ccu CLK_DRAM_CSI0>;
382 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;