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Searched full:clk2 (Results 1 – 25 of 40) sorted by relevance

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/linux/drivers/clocksource/
H A Dtimer-sp804.c259 struct clk *clk1, *clk2; in sp804_of_init() local
284 clk2 = of_clk_get(np, 1); in sp804_of_init()
285 if (IS_ERR(clk2)) { in sp804_of_init()
287 (int)PTR_ERR(clk2)); in sp804_of_init()
288 clk2 = NULL; in sp804_of_init()
291 clk2 = clk1; in sp804_of_init()
302 ret = sp804_clockevents_init(timer2_base, irq, clk2, name); in sp804_of_init()
317 name, clk2, 1); in sp804_of_init()
/linux/drivers/clk/ti/
H A Dclk-33xx.c274 struct clk *clk1, *clk2; in am33xx_dt_clk_init() local
295 clk2 = clk_get_sys(NULL, "timer3_fck"); in am33xx_dt_clk_init()
296 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
298 clk2 = clk_get_sys(NULL, "timer6_fck"); in am33xx_dt_clk_init()
299 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
308 clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); in am33xx_dt_clk_init()
309 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
/linux/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c124 struct clk *clk2; member
267 ret = clk_prepare_enable(phy->clk2); in sun4i_usb_phy_init()
275 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
287 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
296 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
305 ret = clk_prepare_enable(phy2->clk2); in sun4i_usb_phy_init()
310 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
321 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
396 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_exit()
826 phy->clk2 = devm_clk_get(dev, name); in sun4i_usb_phy_probe()
[all …]
/linux/sound/soc/codecs/
H A Dpcm3060.h20 /* ADC and DAC can be clocked from separate or same sources CLK1 and CLK2 */
21 #define PCM3060_CLK_DEF 0 /* default: CLK1->ADC, CLK2->DAC */
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4377.yaml53 clk2-enable-gpios:
85 clk2-enable-gpios: false
/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml273 hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
281 hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
341 pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
361 pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml106 csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
114 csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
/linux/sound/soc/qcom/
H A Dlpass-apq8016.c275 "mi2s-osr-clk2",
281 "mi2s-bit-clk2",
/linux/include/dt-bindings/clock/
H A Dintel,lgm-clk.h134 /* Gate CLK2 */
/linux/arch/powerpc/platforms/8xx/
H A Dtqm8xx_setup.c56 {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
H A Dmpc86xads_setup.c48 {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
H A Dep88xc.c76 {0, 6, CPM_PIN_INPUT}, /* CLK2 */
/linux/drivers/clk/renesas/
H A Dr9a08g045-cpg.c54 #define G3S_PLL146_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12 | (setting)) argument
H A Drzv2h-cpg.c225 unsigned int clk1, clk2; in rzv2h_cpg_pll_clk_recalc_rate() local
232 clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset)); in rzv2h_cpg_pll_clk_recalc_rate()
235 CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2)); in rzv2h_cpg_pll_clk_recalc_rate()
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml151 - const: mi2s-bit-clk2
/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml257 * Overwrite CLK2 configuration with:
/linux/drivers/clk/sunxi-ng/
H A Dccu-suniv-f1c100s.c294 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
297 static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
/linux/drivers/video/fbdev/
H A Dpxa168fb.c234 * clk2 = clk_in / integer_divider
235 * clk_out = clk2 * (1 - (fractional_divider >> 12))
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-colibri.dtsi259 clk2-out-pw5 {
620 clk2-req-pcc5 {
H A Dtegra30-apalis.dtsi151 clk2-out-pw5 {
445 clk2-req-pcc5 {
H A Dtegra30-apalis-v1.1.dtsi152 clk2-out-pw5 {
446 clk2-req-pcc5 {
/linux/drivers/soc/tegra/
H A Dpmc.c3499 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3532 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3636 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3746 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3787 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3943 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3995 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
/linux/drivers/bus/
H A Domap_l3_noc.h295 {0x800000, "HOST CLK2",},
/linux/sound/soc/renesas/
H A Drz-ssi.c1099 "no audio clk2"); in rz_ssi_probe()
1104 "no audio clk1 or audio clk2"); in rz_ssi_probe()
/linux/drivers/clk/
H A Dclk-npcm7xx.c197 #define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/

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