Home
last modified time | relevance | path

Searched full:cgu (Results 1 – 25 of 69) sorted by relevance

123

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dingenic,cgu.yaml4 $id: http://devicetree.org/schemas/clock/ingenic,cgu.yaml#
7 title: Ingenic SoCs CGU
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4755-cgu
26 - ingenic,jz4760-cgu
27 - ingenic,jz4760b-cgu
28 - ingenic,jz4770-cgu
29 - ingenic,jz4780-cgu
[all …]
H A Dlpc1850-ccu.txt3 Each CGU base clock has several clock branches which can be turned on
23 from the CGU to the specific CCU. See mapping of base clocks
27 from the CGU to the specific CCU. Valid CCU clock names:
47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CL
[all...]
H A Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
3 The CGU generates multiple independent clocks for the core and the
9 The CGU selects the inputs to the clock generators from multiple
23 Should be "nxp,lpc1850-cgu"
32 sources to the CGU. The list shall be in the following
36 number provided by the CGU.
39 the clocks provided by the CGU.
41 Which base clocks that are available on the CGU depends on the
116 cgu: clock-controller@40050000 {
117 compatible = "nxp,lpc1850-cgu";
[all …]
H A Dintel,cgu-lgm.yaml4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
7 title: Intel Lightning Mountain SoC's Clock Controller(CGU)
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
14 all means to access the CGU hardware module in order to generate a series
23 const: intel,cgu-lgm
40 cgu: clock-controller@e0200000 {
41 compatible = "intel,cgu-lgm";
/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Djz4770.dtsi2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
19 clocks = <&cgu JZ4770_CLK_CCLK>;
53 cgu: jz4770-cgu@10000000 { label
54 compatible = "ingenic,jz4770-cgu", "simple-mfd";
69 clocks = <&cgu JZ4770_CLK_OTG_PHY>;
84 clocks = <&cgu JZ4770_CLK_RTC>,
85 <&cgu JZ4770_CLK_EXT>,
86 <&cgu JZ4770_CLK_PCLK>;
241 clocks = <&cgu JZ4770_CLK_AI
[all...]
H A Djz4740.dtsi2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
19 clocks = <&cgu JZ4740_CLK_CCLK>;
53 cgu: jz4740-cgu@10000000 { label
54 compatible = "ingenic,jz4740-cgu";
72 clocks = <&cgu JZ4740_CLK_RTC>,
73 <&cgu JZ4740_CLK_EXT>,
74 <&cgu JZ4740_CLK_PCLK>,
75 <&cgu JZ4740_CLK_TCU>;
114 clocks = <&cgu JZ4740_CLK_RTC>;
195 clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>;
[all …]
H A Djz4780.dtsi2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
20 clocks = <&cgu JZ4780_CLK_CPU>;
29 clocks = <&cgu JZ4780_CLK_CORE1>;
63 cgu: jz4780-cgu@10000000 { label
64 compatible = "ingenic,jz4780-cgu", "simple-mfd";
79 clocks = <&cgu JZ4780_CLK_OTG1>;
105 clocks = <&cgu JZ4780_CLK_RTCLK>,
106 <&cgu JZ4780_CLK_EXCLK>,
107 <&cgu JZ4780_CLK_PCLK>;
156 clocks = <&cgu JZ4780_CLK_RTCLK>;
[all …]
H A Dx1000.dtsi3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
20 clocks = <&cgu X1000_CLK_CPU>;
54 cgu: x1000-cgu@10000000 { label
55 compatible = "ingenic,x1000-cgu", "simple-mfd";
70 clocks = <&cgu X1000_CLK_OTGPHY>;
96 clocks = <&cgu X1000_CLK_OST>;
112 clocks = <&cgu X1000_CLK_RTCLK>,
113 <&cgu X1000_CLK_EXCLK>,
114 <&cgu X1000_CLK_PCLK>,
115 <&cgu X1000_CLK_TCU>;
[all …]
H A Dx1830.dtsi3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
20 clocks = <&cgu X1830_CLK_CPU>;
54 cgu: x1830-cgu@10000000 { label
55 compatible = "ingenic,x1830-cgu", "simple-mfd";
70 clocks = <&cgu X1830_CLK_OTGPHY>;
89 clocks = <&cgu X1830_CLK_OST>;
105 clocks = <&cgu X1830_CLK_RTCLK>,
106 <&cgu X1830_CLK_EXCLK>,
107 <&cgu X1830_CLK_PCLK>,
108 <&cgu X1830_CLK_TCU>;
[all …]
H A Djz4725b.dtsi2 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
19 clocks = <&cgu JZ4725B_CLK_CCLK>;
53 cgu: clock-controller@10000000 { label
54 compatible = "ingenic,jz4725b-cgu";
72 clocks = <&cgu JZ4725B_CLK_RTC>,
73 <&cgu JZ4725B_CLK_EXT>,
74 <&cgu JZ4725B_CLK_PCLK>,
75 <&cgu JZ4725B_CLK_TCU>;
123 clocks = <&cgu JZ4725B_CLK_RTC>;
201 clocks = <&cgu JZ4725B_CLK_AI
[all...]
H A Dgcw0.dts440 &cgu {
451 <&cgu JZ4770_CLK_PLL1>,
452 <&cgu JZ4770_CLK_GPU>,
453 <&cgu JZ4770_CLK_RTC>,
454 <&cgu JZ4770_CLK_UHC>,
455 <&cgu JZ4770_CLK_LPCLK_MUX>,
456 <&cgu JZ4770_CLK_MMC0_MUX>,
457 <&cgu JZ4770_CLK_MMC1_MUX>;
460 <&cgu JZ4770_CLK_PLL0>,
461 <&cgu JZ4770_CLK_OSC32K>,
[all …]
H A Dci20.dts164 &cgu {
169 assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
170 <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,
171 <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_MSCMUX>;
172 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
173 <&cgu JZ4780_CLK_MPLL>,
174 <&cgu JZ4780_CLK_SSIPLL>,
175 <0>, <&cgu JZ4780_CLK_MPLL>;
H A Drs90.dts171 clocks = <&cgu JZ4725B_CLK_UDC_PHY>;
296 &cgu {
298 assigned-clocks = <&cgu JZ4725B_CLK_RTC>;
299 assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>;
308 assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc18xx.dtsi16 #include "dt-bindings/clock/lpc18xx-cgu.h"
165 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
232 cgu: clock-controller@40050000 { label
233 compatible = "nxp,lpc1850-cgu";
243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CL
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mips/lantiq/
H A Dlantiq,cgu.yaml4 $id: http://devicetree.org/schemas/mips/lantiq/lantiq,cgu.yaml#
7 title: Lantiq Xway SoC series Clock Generation Unit (CGU)
16 - lantiq,cgu-xway
29 cgu@103000 {
30 compatible = "lantiq,cgu-xway";
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dingenic,lcd.yaml93 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
101 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
112 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
120 clocks = <&cgu JZ4725B_CLK_LCD>;
/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dingenic,rtc.yaml89 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
97 clocks = <&cgu JZ4740_CLK_RTC>;
102 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
110 clocks = <&cgu JZ4780_CLK_RTCLK>;
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dingenic,mmc.yaml65 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
74 clocks = <&cgu JZ4780_CLK_MSC0>;
85 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
99 clocks = <&cgu JZ4780_CLK_MSC1>;
/freebsd/sys/contrib/device-tree/Bindings/mips/ingenic/
H A Dingenic,cpu.yaml47 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
58 clocks = <&cgu JZ4780_CLK_CPU>;
66 clocks = <&cgu JZ4780_CLK_CORE1>;
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dlantiq,pinctrl-xway.txt51 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
62 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
74 spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
89 spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
101 spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dingenic,vpu.yaml61 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
72 clocks = <&cgu JZ4770_CLK_AUX>, <&cgu JZ4770_CLK_VPU>;
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dingenic,jz4780-hdmi.yaml52 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
60 clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dingenic,aic.yaml74 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
84 clocks = <&cgu JZ4740_CLK_AIC>,
85 <&cgu JZ4740_CLK_I2S>;
/freebsd/sys/contrib/device-tree/Bindings/mips/
H A Dcpus.yaml94 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
105 clocks = <&cgu JZ4780_CLK_CPU>;
113 clocks = <&cgu JZ4780_CLK_CORE1>;
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dingenic,tcu.yaml245 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
256 clocks = <&cgu JZ4770_CLK_RTC>,
257 <&cgu JZ4770_CLK_EXT>,
258 <&cgu JZ4770_CLK_PCLK>;

123