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/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.c22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
38 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
40 cfg |= GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
42 cfg &= ~GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
43 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
48 u32 cfg; in gsc_hw_set_gsc_irq_enable() local
50 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.c21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
29 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
30 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
34 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
35 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
[all …]
H A Dfimc-lite-reg.c23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
31 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) in flite_hw_reset()
36 cfg |= FLITE_REG_CIGCTRL_SWRST; in flite_hw_reset()
37 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq() local
43 cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; in flite_hw_clear_pending_irq()
[all …]
/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
42 cfg->clk_prepare = 38000; in phy_mipi_dphy_calc_config()
43 cfg->clk_settle = 95000; in phy_mipi_dphy_calc_config()
44 cfg->clk_term_en = 0; in phy_mipi_dphy_calc_config()
45 cfg->clk_trail = 60000; in phy_mipi_dphy_calc_config()
46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()
[all …]
/linux/tools/testing/selftests/drivers/net/hw/
H A Drss_ctx.py23 def _rss_key_check(cfg, data=None, context=0): argument
25 data = get_rss(cfg, context=context)
32 def get_rss(cfg, context=0): argument
33 return ethtool(f"-x {cfg.ifname} context {context}", json=True)[0]
36 def get_drop_err_sum(cfg): argument
37 stats = ip("-s -s link show dev " + cfg.ifname, json=True)[0]
46 def ethtool_create(cfg, act, opts): argument
47 output = ethtool(f"{act} {cfg.ifname} {opts}").stdout
53 def require_ntuple(cfg): argument
54 features = ethtool(f"-k {cfg.ifname}", json=True)[0]
[all …]
H A Dcsum.py12 def test_receive(cfg, ipv4=False, extra_args=None): argument
14 if not cfg.have_rx_csum:
15 raise KsftSkipEx(f"Test requires rx checksum offload on {cfg.ifname}")
18 ip_args = f"-4 -S {cfg.remote_v4} -D {cfg.v4}"
20 ip_args = f"-6 -S {cfg.remote_v6} -D {cfg.v6}"
22 rx_cmd = f"{cfg.bin_local} -i {cfg.ifname} -n 100 {ip_args} -r 1 -R {extra_args}"
23 tx_cmd = f"{cfg.bin_remote} -i {cfg.ifname} -n 100 {ip_args} -r 1 -T {extra_args}"
27 cmd(tx_cmd, host=cfg.remote)
30 def test_transmit(cfg, ipv4=False, extra_args=None): argument
32 if (not cfg.have_tx_csum_generic and
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.c18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
28 cfg |= CIGCTRL_IRQ_LEVEL; in camif_hw_reset()
29 camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg); in camif_hw_reset()
32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
33 cfg &= ~CIGCTRL_SWRST; in camif_hw_reset()
[all …]
/linux/tools/testing/selftests/bpf/prog_tests/
H A Dcore_extern.c21 #define CFG "CONFIG_BPF_SYSCALL=n\n" macro
25 const char *cfg; member
32 .cfg = "CONFIG_BPF_SYSCALL=n\n"
54 { .name = "tristate (y)", .cfg = CFG"CONFIG_TRISTATE=y\n",
56 { .name = "tristate (n)", .cfg = CFG"CONFIG_TRISTATE=n\n",
58 { .name = "tristate (m)", .cfg = CFG"CONFIG_TRISTATE=m\n",
60 { .name = "tristate (int)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=1" },
61 { .name = "tristate (bad)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=M" },
63 { .name = "bool (y)", .cfg = CFG"CONFIG_BOOL=y\n",
65 { .name = "bool (n)", .cfg = CFG"CONFIG_BOOL=n\n",
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.c133 u64 cfg, last; in rpm_lmac_tx_enable() local
138 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
139 last = cfg; in rpm_lmac_tx_enable()
141 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
143 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
145 if (cfg != last) in rpm_lmac_tx_enable()
146 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
153 u64 cfg; in rpm_lmac_rx_tx_enable() local
158 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_rx_tx_enable()
160 cfg |= RPM_RX_EN | RPM_TX_EN; in rpm_lmac_rx_tx_enable()
[all …]
H A Dcgx.c210 u64 cfg; in cgx_lmac_get_p2x() local
212 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG); in cgx_lmac_get_p2x()
214 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT; in cgx_lmac_get_p2x()
258 u64 cfg; in cgx_lmac_addr_set() local
267 /* memcpy(&cfg, mac_addr, 6); */ in cgx_lmac_addr_set()
269 cfg = ether_addr_to_u64(mac_addr); in cgx_lmac_addr_set()
276 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); in cgx_lmac_addr_set()
278 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); in cgx_lmac_addr_set()
279 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE | in cgx_lmac_addr_set()
281 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); in cgx_lmac_addr_set()
[all …]
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8998.c283 struct hdmi_8998_phy_pll_reg_cfg *cfg) in pll_calculate() argument
330 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
332 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
334 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
335 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
336 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
337 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
338 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
339 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
340 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
H A Dhdmi_phy_8996.c219 struct hdmi_8996_phy_pll_reg_cfg *cfg) in pll_calculate() argument
286 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
288 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
290 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
291 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
292 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
293 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
294 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
295 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
296 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
166 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
167 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | in fimc_set_type_ctrl()
174 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | in fimc_set_type_ctrl()
179 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
184 u32 cfg; in fimc_handle_jpeg() local
188 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_handle_jpeg()
[all …]
H A Dexynos_drm_gsc.c66 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) argument
381 u32 cfg; in gsc_sw_reset() local
385 cfg = (GSC_SW_RESET_SRESET); in gsc_sw_reset()
386 gsc_write(cfg, GSC_SW_RESET); in gsc_sw_reset()
390 cfg = gsc_read(GSC_SW_RESET); in gsc_sw_reset()
391 if (!cfg) in gsc_sw_reset()
396 if (cfg) { in gsc_sw_reset()
402 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
403 cfg |= (GSC_IN_BASE_ADDR_MASK | in gsc_sw_reset()
405 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
63 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
67 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
68 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
69 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
70 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) argument
[all …]
/linux/drivers/net/wireless/microchip/wilc1000/
H A Dwlan_cfg.c142 struct wilc_cfg *cfg = &wl->cfg; in wilc_wlan_parse_response_frame() local
150 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) in wilc_wlan_parse_response_frame()
153 if (cfg->b[i].id == wid) in wilc_wlan_parse_response_frame()
154 cfg->b[i].val = info[4]; in wilc_wlan_parse_response_frame()
160 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) in wilc_wlan_parse_response_frame()
163 if (cfg->hw[i].id == wid) in wilc_wlan_parse_response_frame()
164 cfg->hw[i].val = get_unaligned_le16(&info[4]); in wilc_wlan_parse_response_frame()
170 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) in wilc_wlan_parse_response_frame()
173 if (cfg->w[i].id == wid) in wilc_wlan_parse_response_frame()
174 cfg->w[i].val = get_unaligned_le32(&info[4]); in wilc_wlan_parse_response_frame()
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val argument
131 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) argument
132 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr) argument
[all …]
/linux/drivers/scsi/cxlflash/
H A Dmain.c50 struct cxlflash_cfg *cfg = afu->parent; in process_cmd_err() local
51 struct device *dev = &cfg->dev->dev; in process_cmd_err()
162 struct cxlflash_cfg *cfg = afu->parent; in cmd_complete() local
163 struct device *dev = &cfg->dev->dev; in cmd_complete()
181 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in cmd_complete()
182 cfg->tmf_active = false; in cmd_complete()
183 wake_up_all_locked(&cfg->tmf_waitq); in cmd_complete()
184 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); in cmd_complete()
198 struct cxlflash_cfg *cfg = hwq->afu->parent; in flush_pending_cmds() local
218 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in flush_pending_cmds()
[all …]
/linux/drivers/leds/
H A Dleds-lp55xx-common.c92 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_wait_opmode_done() local
101 if (cfg->engine_busy.val) { in lp55xx_wait_opmode_done()
102 read_poll_timeout(lp55xx_read, ret, !(val & cfg->engine_busy.mask), in lp55xx_wait_opmode_done()
104 chip, cfg->engine_busy.addr, &val); in lp55xx_wait_opmode_done()
112 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_stop_all_engine() local
114 lp55xx_write(chip, cfg->reg_op_mode.addr, LP55xx_MODE_DISABLE_ALL_ENG); in lp55xx_stop_all_engine()
122 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_load_engine() local
125 mask = LP55xx_MODE_ENGn_MASK(idx, cfg->reg_op_mode.shift); in lp55xx_load_engine()
126 val = LP55xx_MODE_LOAD_ENG << LP55xx_MODE_ENGn_SHIFT(idx, cfg->reg_op_mode.shift); in lp55xx_load_engine()
128 lp55xx_update_bits(chip, cfg->reg_op_mode.addr, mask, val); in lp55xx_load_engine()
[all …]
/linux/sound/soc/intel/avs/
H A Dpath.c148 struct avs_copier_cfg *cfg; in avs_copier_create() local
157 data_size = sizeof(cfg->gtw_cfg.config); in avs_copier_create()
241 cfg = adev->modcfg_buf; in avs_copier_create()
242 memset(cfg, 0, cfg_size); in avs_copier_create()
243 cfg->base.cpc = t->cfg_base->cpc; in avs_copier_create()
244 cfg->base.ibs = t->cfg_base->ibs; in avs_copier_create()
245 cfg->base.obs = t->cfg_base->obs; in avs_copier_create()
246 cfg->base.is_pages = t->cfg_base->is_pages; in avs_copier_create()
247 cfg->base.audio_fmt = *t->in_fmt; in avs_copier_create()
248 cfg->out_fmt = *t->cfg_ext->copier.out_fmt; in avs_copier_create()
[all …]
/linux/drivers/staging/media/atomisp/pci/runtime/isys/src/
H A Dvirtual_isys.c27 isp2401_input_system_cfg_t *cfg,
35 isp2401_input_system_cfg_t *cfg,
95 pixelgen_prbs_cfg_t *cfg);
99 csi_rx_frontend_cfg_t *cfg);
105 csi_rx_backend_cfg_t *cfg);
110 stream2mmio_cfg_t *cfg);
116 ibuf_ctrl_cfg_t *cfg);
121 isys2401_dma_cfg_t *cfg);
127 isys2401_dma_port_cfg_t *cfg);
264 isp2401_input_system_cfg_t *cfg, in create_input_system_channel() argument
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_config.h56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
59 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
61 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
63 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
64 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
65 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
66 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) argument
[all …]
/linux/arch/loongarch/pci/
H A Dacpi.c19 struct pci_config_window *cfg; member
31 struct pci_config_window *cfg = bridge->bus->sysdata; in pcibios_root_bridge_prepare() local
34 adev = to_acpi_device(cfg->parent); in pcibios_root_bridge_prepare()
37 set_dev_node(bus_dev, pa_to_nid(cfg->res.start)); in pcibios_root_bridge_prepare()
44 struct pci_config_window *cfg = bus->sysdata; in acpi_pci_bus_find_domain_nr() local
45 struct acpi_device *adev = to_acpi_device(cfg->parent); in acpi_pci_bus_find_domain_nr()
56 pci_ecam_free(info->cfg); in acpi_release_root_info()
99 struct pci_config_window *cfg; in arch_pci_ecam_create() local
104 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); in arch_pci_ecam_create()
105 if (!cfg) in arch_pci_ecam_create()
[all …]
/linux/net/bridge/
H A Dbr_mdb.c721 static int br_mdb_replace_group_sg(const struct br_mdb_config *cfg, in br_mdb_replace_group_sg() argument
730 pg->rt_protocol = cfg->rt_protocol; in br_mdb_replace_group_sg()
731 if (!(flags & MDB_PG_FLAGS_PERMANENT) && !cfg->src_entry) in br_mdb_replace_group_sg()
737 br_mdb_notify(cfg->br->dev, mp, pg, RTM_NEWMDB); in br_mdb_replace_group_sg()
742 static int br_mdb_add_group_sg(const struct br_mdb_config *cfg, in br_mdb_add_group_sg() argument
753 (p = mlock_dereference(*pp, cfg->br)) != NULL; in br_mdb_add_group_sg()
755 if (p->key.port == cfg->p) { in br_mdb_add_group_sg()
756 if (!(cfg->nlflags & NLM_F_REPLACE)) { in br_mdb_add_group_sg()
760 return br_mdb_replace_group_sg(cfg, mp, p, brmctx, in br_mdb_add_group_sg()
763 if ((unsigned long)p->key.port < (unsigned long)cfg->p) in br_mdb_add_group_sg()
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c67 u64 cfg; in xcv_init_hw() local
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
71 cfg &= ~DLL_RESET; in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
76 cfg &= ~CLK_RESET; in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
85 cfg &= ~0xFF03; in xcv_init_hw()
86 cfg |= CLKRX_BYP; in xcv_init_hw()
[all …]

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