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/linux/tools/testing/selftests/drivers/net/
H A Dping.py14 def _test_v4(cfg) -> None: argument
15 if not cfg.addr_v["4"]:
18 cmd("ping -c 1 -W0.5 " + cfg.remote_addr_v["4"])
19 cmd("ping -c 1 -W0.5 " + cfg.addr_v["4"], host=cfg.remote)
20 cmd("ping -s 65000 -c 1 -W0.5 " + cfg.remote_addr_v["4"])
21 cmd("ping -s 65000 -c 1 -W0.5 " + cfg.addr_v["4"], host=cfg.remote)
23 def _test_v6(cfg) -> None: argument
24 if not cfg.addr_v["6"]:
27 cmd("ping -c 1 -W5 " + cfg.remote_addr_v["6"])
28 cmd("ping -c 1 -W5 " + cfg.addr_v["6"], host=cfg.remote)
[all …]
H A Dhds.py12 def _get_hds_mode(cfg, netnl) -> str: argument
14 rings = netnl.rings_get({'header': {'dev-index': cfg.ifindex}})
22 def _xdp_onoff(cfg): argument
23 prog = cfg.net_lib_dir / "xdp_dummy.bpf.o"
25 (cfg.ifname, prog))
26 ip("link set dev %s xdp off" % cfg.ifname)
29 def _ioctl_ringparam_modify(cfg, netnl) -> None: argument
35 rings = netnl.rings_get({'header': {'dev-index': cfg.ifindex}})
43 ethtool(f"--disable-netlink -G {cfg.ifname} tx {rings['tx'] // 2}")
45 ethtool(f"--disable-netlink -G {cfg.ifname} tx {rings['tx'] * 2}")
[all …]
/linux/tools/testing/selftests/drivers/net/hw/
H A Diou-zcrx.py11 def _get_current_settings(cfg): argument
12 output = ethtool(f"-g {cfg.ifname}", json=True, host=cfg.remote)[0]
16 def _get_combined_channels(cfg): argument
17 output = ethtool(f"-l {cfg.ifname}", host=cfg.remote).stdout
22 def _create_rss_ctx(cfg, chan): argument
23 output = ethtool(f"-X {cfg.ifname} context new start {chan} equal 1", host=cfg.remote).stdout
26 return (ctx_id, defer(ethtool, f"-X {cfg.ifname} delete context {ctx_id}", host=cfg.remote))
29 def _set_flow_rule(cfg, port, chan): argument
30 …output = ethtool(f"-N {cfg.ifname} flow-type tcp6 dst-port {port} action {chan}", host=cfg.remote)…
35 def _set_flow_rule_rss(cfg, port, ctx_id): argument
[all …]
H A Drss_ctx.py24 def _rss_key_check(cfg, data=None, context=0): argument
26 data = get_rss(cfg, context=context)
33 def get_rss(cfg, context=0): argument
34 return ethtool(f"-x {cfg.ifname} context {context}", json=True)[0]
37 def get_drop_err_sum(cfg): argument
38 stats = ip("-s -s link show dev " + cfg.ifname, json=True)[0]
47 def ethtool_create(cfg, act, opts): argument
48 output = ethtool(f"{act} {cfg.ifname} {opts}").stdout
54 def require_ntuple(cfg): argument
55 features = ethtool(f"-k {cfg.ifname}", json=True)[0]
[all …]
H A Dtso.py36 def run_one_stream(cfg, ipver, remote_v4, remote_v6, should_lso): argument
37 cfg.require_cmd("socat", remote=True)
42 with bkg(listen_cmd, host=cfg.remote, exit_wait=True) as nc:
43 wait_port_listen(port, host=cfg.remote)
57 qstat_old = cfg.netnl.qstats_get({"ifindex": cfg.ifindex}, dump=True)[0]
61 qstat_new = cfg.netnl.qstats_get({"ifindex": cfg.ifindex}, dump=True)[0]
71 total_lso_wire = len(buf) * 0.90 // cfg.dev["mtu"]
72 total_lso_super = len(buf) * 0.90 // cfg.dev["tso_max_size"]
74 if cfg.have_stat_super_count:
79 if cfg.have_stat_wire_count:
[all …]
/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.c22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
38 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
40 cfg |= GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
42 cfg &= ~GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
43 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
48 u32 cfg; in gsc_hw_set_gsc_irq_enable() local
50 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.c21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
29 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
30 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
34 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
35 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
[all …]
H A Dfimc-lite-reg.c23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
31 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) in flite_hw_reset()
36 cfg |= FLITE_REG_CIGCTRL_SWRST; in flite_hw_reset()
37 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq() local
43 cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; in flite_hw_clear_pending_irq()
[all …]
/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
42 cfg->clk_prepare = 38000; in phy_mipi_dphy_calc_config()
43 cfg->clk_settle = 95000; in phy_mipi_dphy_calc_config()
44 cfg->clk_term_en = 0; in phy_mipi_dphy_calc_config()
45 cfg->clk_trail = 60000; in phy_mipi_dphy_calc_config()
46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.c18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
28 cfg |= CIGCTRL_IRQ_LEVEL; in camif_hw_reset()
29 camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg); in camif_hw_reset()
32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
33 cfg &= ~CIGCTRL_SWRST; in camif_hw_reset()
[all …]
/linux/tools/testing/selftests/bpf/prog_tests/
H A Dcore_extern.c21 #define CFG "CONFIG_BPF_SYSCALL=n\n" macro
25 const char *cfg; member
32 .cfg = "CONFIG_BPF_SYSCALL=n\n"
54 { .name = "tristate (y)", .cfg = CFG"CONFIG_TRISTATE=y\n",
56 { .name = "tristate (n)", .cfg = CFG"CONFIG_TRISTATE=n\n",
58 { .name = "tristate (m)", .cfg = CFG"CONFIG_TRISTATE=m\n",
60 { .name = "tristate (int)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=1" },
61 { .name = "tristate (bad)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=M" },
63 { .name = "bool (y)", .cfg = CFG"CONFIG_BOOL=y\n",
65 { .name = "bool (n)", .cfg = CFG"CONFIG_BOOL=n\n",
[all …]
/linux/drivers/pci/
H A Decam.c32 struct pci_config_window *cfg; in pci_ecam_create() local
40 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); in pci_ecam_create()
41 if (!cfg) in pci_ecam_create()
48 cfg->parent = dev; in pci_ecam_create()
49 cfg->ops = ops; in pci_ecam_create()
50 cfg->busr.start = busr->start; in pci_ecam_create()
51 cfg->busr.end = busr->end; in pci_ecam_create()
52 cfg->busr.flags = IORESOURCE_BUS; in pci_ecam_create()
53 cfg->bus_shift = bus_shift; in pci_ecam_create()
54 bus_range = resource_size(&cfg->busr); in pci_ecam_create()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.c133 u64 cfg, last; in rpm_lmac_tx_enable() local
138 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
139 last = cfg; in rpm_lmac_tx_enable()
141 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
143 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
145 if (cfg != last) in rpm_lmac_tx_enable()
146 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
153 u64 cfg; in rpm_lmac_rx_tx_enable() local
158 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_rx_tx_enable()
160 cfg |= RPM_RX_EN | RPM_TX_EN; in rpm_lmac_rx_tx_enable()
[all …]
H A Dcgx.c220 u64 cfg; in cgx_lmac_get_p2x() local
222 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG); in cgx_lmac_get_p2x()
224 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT; in cgx_lmac_get_p2x()
268 u64 cfg; in cgx_lmac_addr_set() local
277 /* memcpy(&cfg, mac_addr, 6); */ in cgx_lmac_addr_set()
279 cfg = ether_addr_to_u64(mac_addr); in cgx_lmac_addr_set()
286 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); in cgx_lmac_addr_set()
288 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); in cgx_lmac_addr_set()
289 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE | in cgx_lmac_addr_set()
291 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); in cgx_lmac_addr_set()
[all …]
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8998.c283 struct hdmi_8998_phy_pll_reg_cfg *cfg) in pll_calculate() argument
330 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
332 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
334 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
335 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
336 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
337 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
338 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
339 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
340 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
H A Dhdmi_phy_8996.c219 struct hdmi_8996_phy_pll_reg_cfg *cfg) in pll_calculate() argument
286 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
288 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
290 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
291 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
292 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
293 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
294 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
295 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
296 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
/linux/sound/pci/hda/
H A Dhda_auto_parser.c55 /* add the found input-pin to the cfg->inputs[] table */
56 static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, in add_auto_cfg_input_pin() argument
59 if (cfg->num_inputs < AUTO_CFG_MAX_INS) { in add_auto_cfg_input_pin()
60 cfg->inputs[cfg->num_inputs].pin = nid; in add_auto_cfg_input_pin()
61 cfg->inputs[cfg->num_inputs].type = type; in add_auto_cfg_input_pin()
62 cfg->inputs[cfg->num_inputs].has_boost_on_pin = in add_auto_cfg_input_pin()
64 cfg->num_inputs++; in add_auto_cfg_input_pin()
156 * Parse all pin widgets and store the useful pin nids to cfg
173 struct auto_pin_cfg *cfg, in snd_hda_parse_pin_defcfg() argument
179 struct auto_out_pin line_out[ARRAY_SIZE(cfg->line_out_pins)]; in snd_hda_parse_pin_defcfg()
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
166 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
167 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | in fimc_set_type_ctrl()
174 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | in fimc_set_type_ctrl()
179 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
184 u32 cfg; in fimc_handle_jpeg() local
188 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_handle_jpeg()
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
63 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
67 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
68 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
69 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
70 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) argument
[all …]
/linux/drivers/net/wireless/microchip/wilc1000/
H A Dwlan_cfg.c142 struct wilc_cfg *cfg = &wl->cfg; in wilc_wlan_parse_response_frame() local
150 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) in wilc_wlan_parse_response_frame()
153 if (cfg->b[i].id == wid) in wilc_wlan_parse_response_frame()
154 cfg->b[i].val = info[4]; in wilc_wlan_parse_response_frame()
160 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) in wilc_wlan_parse_response_frame()
163 if (cfg->hw[i].id == wid) in wilc_wlan_parse_response_frame()
164 cfg->hw[i].val = get_unaligned_le16(&info[4]); in wilc_wlan_parse_response_frame()
170 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) in wilc_wlan_parse_response_frame()
173 if (cfg->w[i].id == wid) in wilc_wlan_parse_response_frame()
174 cfg->w[i].val = get_unaligned_le32(&info[4]); in wilc_wlan_parse_response_frame()
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val argument
131 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) argument
132 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr) argument
[all …]
/linux/drivers/leds/
H A Dleds-lp55xx-common.c92 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_wait_opmode_done() local
101 if (cfg->engine_busy.val) { in lp55xx_wait_opmode_done()
102 read_poll_timeout(lp55xx_read, ret, !(val & cfg->engine_busy.mask), in lp55xx_wait_opmode_done()
104 chip, cfg->engine_busy.addr, &val); in lp55xx_wait_opmode_done()
112 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_stop_all_engine() local
114 lp55xx_write(chip, cfg->reg_op_mode.addr, LP55xx_MODE_DISABLE_ALL_ENG); in lp55xx_stop_all_engine()
122 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_load_engine() local
125 mask = LP55xx_MODE_ENGn_MASK(idx, cfg->reg_op_mode.shift); in lp55xx_load_engine()
126 val = LP55xx_MODE_LOAD_ENG << LP55xx_MODE_ENGn_SHIFT(idx, cfg->reg_op_mode.shift); in lp55xx_load_engine()
128 lp55xx_update_bits(chip, cfg->reg_op_mode.addr, mask, val); in lp55xx_load_engine()
[all …]
/linux/drivers/staging/media/atomisp/pci/runtime/isys/src/
H A Dvirtual_isys.c27 isp2401_input_system_cfg_t *cfg,
35 isp2401_input_system_cfg_t *cfg,
95 pixelgen_prbs_cfg_t *cfg);
99 csi_rx_frontend_cfg_t *cfg);
105 csi_rx_backend_cfg_t *cfg);
110 stream2mmio_cfg_t *cfg);
116 ibuf_ctrl_cfg_t *cfg);
121 isys2401_dma_cfg_t *cfg);
127 isys2401_dma_port_cfg_t *cfg);
264 isp2401_input_system_cfg_t *cfg, in create_input_system_channel() argument
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_config.h56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
59 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
61 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
63 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
64 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
65 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
66 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) argument
[all …]
/linux/drivers/iommu/
H A Dio-pgtable-arm.c236 static inline bool arm_lpae_concat_mandatory(struct io_pgtable_cfg *cfg, in arm_lpae_concat_mandatory() argument
239 unsigned int ias = cfg->ias; in arm_lpae_concat_mandatory()
240 unsigned int oas = cfg->oas; in arm_lpae_concat_mandatory()
261 struct io_pgtable_cfg *cfg, in __arm_lpae_alloc_pages() argument
264 struct device *dev = cfg->iommu_dev; in __arm_lpae_alloc_pages()
274 if (cfg->alloc) in __arm_lpae_alloc_pages()
275 pages = cfg->alloc(cookie, alloc_size, gfp); in __arm_lpae_alloc_pages()
283 if (!cfg->coherent_walk) { in __arm_lpae_alloc_pages()
303 if (cfg->free) in __arm_lpae_alloc_pages()
304 cfg->free(cookie, pages, size); in __arm_lpae_alloc_pages()
[all …]

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