Home
last modified time | relevance | path

Searched +full:cfg +full:- +full:space (Results 1 – 25 of 386) sorted by relevance

12345678910>>...16

/linux/drivers/pci/
H A Decam.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-ecam.h>
15 * On 64-bit systems, we do a single ioremap for the whole config space
16 * since we have enough virtual address range available. On 32-bit, we
17 * ioremap the config space for each bus individually.
22 * Create a PCI config space window
23 * - reserve mem region
24 * - alloc struct pci_config_window with space for all mappings
25 * - ioremap the config space
31 unsigned int bus_shift = ops->bus_shift; in pci_ecam_create()
[all …]
/linux/arch/x86/pci/
H A Dmmconfig_64.c1 // SPDX-License-Identifier: GPL-2.0
3 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
6 * space mapped. This allows lockless config space operation.
21 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in pci_dev_base() local
23 if (cfg && cfg->virt) in pci_dev_base()
24 return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); in pci_dev_base()
33 /* Why do we have this when nobody checks it. How about a BUG()!? -AK */ in pci_mmcfg_read()
35 err: *value = -1; in pci_mmcfg_read()
36 return -EINVAL; in pci_mmcfg_read()
67 /* Why do we have this when nobody checks it. How about a BUG()!? -AK */ in pci_mmcfg_write()
[all …]
H A Dmmconfig_32.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
25 * Functions for accessing PCI configuration space with MMCONFIG accesses
29 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in get_base_addr() local
31 if (cfg) in get_base_addr()
32 return cfg->address; in get_base_addr()
58 err: *value = -1; in pci_mmcfg_read()
59 return -EINVAL; in pci_mmcfg_read()
97 return -EINVAL; in pci_mmcfg_write()
103 return -EINVAL; in pci_mmcfg_write()
[all …]
/linux/arch/loongarch/pci/
H A Dacpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
10 #include <linux/pci-acpi.h>
11 #include <linux/pci-ecam.h>
19 struct pci_config_window *cfg; member
30 struct device *bus_dev = &bridge->bus->dev; in pcibios_root_bridge_prepare()
31 struct pci_config_window *cfg = bridge->bus->sysdata; in pcibios_root_bridge_prepare() local
34 adev = to_acpi_device(cfg->parent); in pcibios_root_bridge_prepare()
36 ACPI_COMPANION_SET(&bridge->dev, adev); in pcibios_root_bridge_prepare()
37 set_dev_node(bus_dev, pa_to_nid(cfg->res.start)); in pcibios_root_bridge_prepare()
[all …]
/linux/include/acpi/
H A Dnhlt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2023-2024 Intel Corporation
18 #define __acpi_nhlt_config_caps(cfg) ((void *)((cfg) + 1)) argument
21 * acpi_nhlt_endpoint_fmtscfg - Get the formats configuration space.
22 * @ep: the endpoint to retrieve the space for.
24 * Return: A pointer to the formats configuration space.
29 struct acpi_nhlt_config *cfg = __acpi_nhlt_endpoint_config(ep); in acpi_nhlt_endpoint_fmtscfg() local
31 return (struct acpi_nhlt_formats_config *)((u8 *)(cfg + 1) + cfg->capabilities_size); in acpi_nhlt_endpoint_fmtscfg()
38 ((void *)((u8 *)(ep) + (ep)->length))
47 ((void *)((u8 *)((fmt) + 1) + (fmt)->config.capabilities_size))
[all …]
/linux/net/core/
H A Ddev_ioctl.c1 // SPDX-License-Identifier: GPL-2.0
26 * match. --pb
31 ifr->ifr_name[IFNAMSIZ-1] = 0; in dev_ifname()
32 return netdev_get_name(net, ifr->ifr_name, ifr->ifr_ifindex); in dev_ifname()
52 return -EFAULT; in dev_ifconf()
61 return -EFAULT; in dev_ifconf()
75 len - total, size); in dev_ifconf()
78 return -EFAULT; in dev_ifconf()
84 return put_user(total, &uifc->ifc_len); in dev_ifconf()
89 struct ifmap *ifmap = &ifr->ifr_map; in dev_getifmap()
[all …]
/linux/arch/sparc/kernel/
H A Dleon_pci_grpci1.c1 // SPDX-License-Identifier: GPL-2.0
32 /* Enable/Disable Debugging Configuration Space Access */
108 struct grpci1_priv *priv = dev->bus->sysdata; in grpci1_map_irq()
113 pin = ((pin - 1) + irq_group) & 0x3; in grpci1_map_irq()
115 return priv->irq_map[pin]; in grpci1_map_irq()
121 u32 *pci_conf, tmp, cfg; in grpci1_cfg_r32() local
124 return -EINVAL; in grpci1_cfg_r32()
134 cfg = REGLOAD(priv->regs->cfg_stat); in grpci1_cfg_r32()
135 REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23)); in grpci1_cfg_r32()
138 pci_conf = (u32 *) (priv->pci_conf | (devfn << 8) | (where & 0xfc)); in grpci1_cfg_r32()
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
36 /* set of registers with offsets different per-PHY */
139 /* struct qmp_phy_cfg - per-PHY initialization config */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
169 * struct qmp_phy - per-lane phy descriptor
172 * @cfg: phy specific configuration
173 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
[all …]
/linux/drivers/tty/
H A Dmips_ejtag_fdc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
80 * and space becoming available in TX FIFO.
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
123 * @ports: Per-channel data.
124 * @waitqueue: Wait queue for waiting for TX data, or for space in TX
133 * @xmit_full: Indicates TX FIFO is full, we're waiting for space.
174 __raw_writel(data, priv->reg + offs); in mips_ejtag_fdc_write()
180 return __raw_readl(priv->reg + offs); in mips_ejtag_fdc_read()
[all …]
/linux/drivers/pci/controller/
H A Dpci-host-common.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/pci-ecam.h>
18 #include "pci-host-common.h"
31 struct pci_config_window *cfg; in pci_host_common_ecam_create() local
33 err = of_address_to_resource(dev->of_node, 0, &cfgres); in pci_host_common_ecam_create()
39 bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); in pci_host_common_ecam_create()
41 return ERR_PTR(-ENODEV); in pci_host_common_ecam_create()
43 cfg = pci_ecam_create(dev, &cfgres, bus->res, ops); in pci_host_common_ecam_create()
44 if (IS_ERR(cfg)) in pci_host_common_ecam_create()
45 return cfg; in pci_host_common_ecam_create()
[all …]
H A Dpci-loongson.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pci-acpi.h>
13 #include <linux/pci-ecam.h>
58 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in bridge_class_quirk()
70 * The address space consumed by these devices is outside the in system_bus_quirk()
73 pdev->mmio_always_on = 1; in system_bus_quirk()
74 pdev->non_compliant_bars = 1; in system_bus_quirk()
93 struct pci_bus *bus = pdev->bus; in loongson_set_min_mrrs_quirk()
109 bridge = bus->self; in loongson_set_min_mrrs_quirk()
110 bus = bus->parent; in loongson_set_min_mrrs_quirk()
[all …]
H A Dpci-thunder-pem.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 - 2016 Cavium, Inc.
12 #include <linux/pci-acpi.h>
13 #include <linux/pci-ecam.h>
15 #include <linux/io-64-nonatomic-lo-hi.h>
17 #include "pci-host-common.h"
27 * N.B. This is a non-standard platform-specific ECAM bus shift value. For
29 * include/linux/pci-ecam.h.
42 struct pci_config_window *cfg = bus->sysdata; in thunder_pem_bridge_read() local
43 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv; in thunder_pem_bridge_read()
[all …]
/linux/drivers/virtio/
H A Dvirtio_pci_modern_dev.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * vp_modern_map_capability - map a part of virtio pci capability
10 * @mdev: the modern virtio-pci device
26 struct pci_dev *dev = mdev->pci_dev; in vp_modern_map_capability()
40 if (bar >= PCI_STD_NUM_BARS || !(mdev->modern_bars & (1 << bar))) { in vp_modern_map_capability()
41 dev_err(&dev->dev, in vp_modern_map_capability()
47 dev_err(&dev->dev, in vp_modern_map_capability()
53 if (length - start < minlen) { in vp_modern_map_capability()
54 dev_err(&dev->dev, in vp_modern_map_capability()
60 length -= start; in vp_modern_map_capability()
[all …]
/linux/drivers/net/ethernet/google/gve/
H A Dgve_tx.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
20 iowrite32be(val, &priv->db_bar2[be32_to_cpu(q_resources->db_index)]); in gve_tx_put_doorbell()
26 struct gve_tx_ring *tx = &priv->tx[tx_qid]; in gve_xdp_tx_flush()
28 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xdp_tx_flush()
35 * gve_tx_fifo_* manages the Registered Segment as a FIFO - clients must
41 fifo->base = vmap(fifo->qpl->pages, fifo->qpl->num_entries, VM_MAP, in gve_tx_fifo_init()
43 if (unlikely(!fifo->base)) { in gve_tx_fifo_init()
44 netif_err(priv, drv, priv->dev, "Failed to vmap fifo, qpl_id = %d\n", in gve_tx_fifo_init()
45 fifo->qpl->id); in gve_tx_fifo_init()
[all …]
/linux/arch/powerpc/kernel/
H A Deeh.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2001-2012 IBM Corporation.
32 #include <asm/ppc-pci.h>
34 #include <asm/pte-walk.h>
40 * usual PCI framework, except by check-stopping the CPU. Systems
41 * that are designed for high-availability/reliability cannot afford
43 * An EEH-capable bridge operates by converting a detected error
44 * into a "slot freeze", taking the PCI adapter off-line, making
50 * vibration, humidity, radioactivity or plain-old failed hardware.
55 * device to bus-master data to a memory address that is not
[all …]
/linux/drivers/gpu/drm/i915/gvt/
H A Dcfg_space.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
45 /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one
46 * byte) byte by byte in standard pci configuration space. (not the full
53 [PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,
59 * vgpu_pci_cfg_mem_write - write virtual cfg space memory
65 * Use this function to write virtual cfg space memory.
66 * For standard cfg space, only RW bits can be changed,
93 /* For other configuration space directly copy as it is. */ in vgpu_pci_cfg_mem_write()
95 memcpy(cfg_base + off + i, src + i, bytes - i); in vgpu_pci_cfg_mem_write()
97 if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) { in vgpu_pci_cfg_mem_write()
[all …]
/linux/arch/riscv/kvm/
H A Dvcpu.c1 // SPDX-License-Identifier: GPL-2.0
57 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_context_reset()
58 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_vcpu_context_reset()
59 void *vector_datap = cntx->vector.datap; in kvm_riscv_vcpu_context_reset()
63 memset(&vcpu->arch.smstateen_csr, 0, sizeof(vcpu->arch.smstateen_csr)); in kvm_riscv_vcpu_context_reset()
66 cntx->vector.datap = vector_datap; in kvm_riscv_vcpu_context_reset()
72 cntx->sstatus = SR_SPP | SR_SPIE; in kvm_riscv_vcpu_context_reset()
74 cntx->hstatus |= HSTATUS_VTW; in kvm_riscv_vcpu_context_reset()
75 cntx->hstatus |= HSTATUS_SPVP; in kvm_riscv_vcpu_context_reset()
76 cntx->hstatus |= HSTATUS_SPV; in kvm_riscv_vcpu_context_reset()
[all …]
/linux/drivers/pci/controller/plda/
H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
21 #include <linux/pci-ecam.h>
26 #include "../pci-host-common.h"
27 #include "pcie-plda.h"
88 /* PCIe Config space MSI capability structure */
301 struct plda_msi *msi = &port->plda.msi; in mc_pcie_enable_msi()
316 writel_relaxed(lower_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
318 writel_relaxed(upper_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
329 u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT); in pcie_events()
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c1 // SPDX-License-Identifier: GPL-2.0-only
67 u64 cfg; in xcv_init_hw() local
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
71 cfg &= ~DLL_RESET; in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
76 cfg &= ~CLK_RESET; in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
81 /* Configure DLL - enable or bypass in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
[all …]
/linux/arch/powerpc/platforms/pasemi/
H A Ddma_lib.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
43 /* pasemi_read_iob_reg - read IOB register
44 * @reg: Register to read (offset into PCI CFG space)
52 /* pasemi_write_iob_reg - write IOB register
53 * @reg: Register to write to (offset into PCI CFG space)
62 /* pasemi_read_mac_reg - read MAC register
64 * @reg: Register to read (offset into PCI CFG space)
72 /* pasemi_write_mac_reg - write MAC register
74 * @reg: Register to write to (offset into PCI CFG space)
[all …]
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_pcie_mac.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2021-2022, Intel Corporation.
20 #include <linux/io-64-nonatomic-lo-hi.h>
82 static int t7xx_pcie_mac_atr_cfg(struct t7xx_pci_dev *t7xx_dev, struct t7xx_atr_config *cfg) in t7xx_pcie_mac_atr_cfg() argument
84 struct device *dev = &t7xx_dev->pdev->dev; in t7xx_pcie_mac_atr_cfg()
90 if (cfg->transparent) { in t7xx_pcie_mac_atr_cfg()
94 if (cfg->src_addr & (cfg->size - 1)) { in t7xx_pcie_mac_atr_cfg()
96 return -EINVAL; in t7xx_pcie_mac_atr_cfg()
99 if (cfg->trsl_addr & (cfg->size - 1)) { in t7xx_pcie_mac_atr_cfg()
101 cfg->trsl_addr, cfg->size - 1); in t7xx_pcie_mac_atr_cfg()
[all …]
/linux/rust/pin-init/internal/src/
H A Dlib.rs1 // SPDX-License-Identifier: Apache-2.0 OR MIT
7 //! `pin-init` proc macros.
11 // - `proc_macro2::TokenStream` into `proc_macro::TokenStream` in the user-space version.
12 // - `proc_macro::TokenStream` into `proc_macro::TokenStream` in the kernel version.
13 // Clippy warns on this conversion, but it's required by the user-space version.
17 // Documentation is done in the pin-init crate instead.
22 #[cfg(kernel)]
27 #[cfg(not(kernel))]
37 pub fn pin_data(inner: TokenStream, item: TokenStream) -> TokenStream { in pin_data()
42 pub fn pinned_drop(args: TokenStream, input: TokenStream) -> TokenStream { in pinned_drop()
[all …]
/linux/rust/kernel/
H A Dmm.rs1 // SPDX-License-Identifier: GPL-2.0
7 //! This module deals with managing the address space of userspace processes. Each process has an
24 #[cfg(CONFIG_MMU)]
30 /// This represents the address space of a userspace process, so each process has one `Mm`
33 /// There is a counter called `mm_users` that counts the users of the address space; this includes
34 /// the userspace process itself, but can also include kernel threads accessing the address space.
35 /// Once `mm_users` reaches zero, this indicates that the address space can be destroyed. To access
36 /// the address space, you must prevent `mm_users` from reaching zero while you are accessing it.
37 /// The [`MmWithUser`] type represents an address space where this is guaranteed, and you can
74 /// This type is like [`Mm`], but with non-zero `mm_users`. It can only be used when `mm_users` can
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dapm,xgene-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apm,xgene-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AppliedMicro X-Gene PCIe interface
10 - Toan Le <toan@os.amperecomputing.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
18 - items:
19 - const: apm,xgene-storm-pcie
20 - const: apm,xgene-pcie
[all …]
H A Dqcom,pcie-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sm8250
25 reg-names:
28 - const: parf # Qualcomm specific registers
29 - const: dbi # DesignWare PCIe registers
[all …]

12345678910>>...16