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/linux/arch/loongarch/pci/
H A Dacpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
10 #include <linux/pci-acpi.h>
11 #include <linux/pci-ecam.h>
19 struct pci_config_window *cfg; member
30 struct device *bus_dev = &bridge->bus->dev; in pcibios_root_bridge_prepare()
31 struct pci_config_window *cfg = bridge->bus->sysdata; in pcibios_root_bridge_prepare() local
34 adev = to_acpi_device(cfg->parent); in pcibios_root_bridge_prepare()
36 ACPI_COMPANION_SET(&bridge->dev, adev); in pcibios_root_bridge_prepare()
37 set_dev_node(bus_dev, pa_to_nid(cfg->res.start)); in pcibios_root_bridge_prepare()
[all …]
/linux/arch/x86/pci/
H A Dmmconfig_64.c1 // SPDX-License-Identifier: GPL-2.0
3 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
6 * space mapped. This allows lockless config space operation.
21 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in pci_dev_base() local
23 if (cfg && cfg->virt) in pci_dev_base()
24 return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); in pci_dev_base()
33 /* Why do we have this when nobody checks it. How about a BUG()!? -AK */ in pci_mmcfg_read()
35 err: *value = -1; in pci_mmcfg_read()
36 return -EINVAL; in pci_mmcfg_read()
67 /* Why do we have this when nobody checks it. How about a BUG()!? -AK */ in pci_mmcfg_write()
[all …]
H A Dmmconfig_32.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
25 * Functions for accessing PCI configuration space with MMCONFIG accesses
29 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in get_base_addr() local
31 if (cfg) in get_base_addr()
32 return cfg->address; in get_base_addr()
58 err: *value = -1; in pci_mmcfg_read()
59 return -EINVAL; in pci_mmcfg_read()
97 return -EINVAL; in pci_mmcfg_write()
103 return -EINVAL; in pci_mmcfg_write()
[all …]
/linux/include/acpi/
H A Dnhlt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2023-2024 Intel Corporation
18 #define __acpi_nhlt_config_caps(cfg) ((void *)((cfg) + 1)) argument
21 * acpi_nhlt_endpoint_fmtscfg - Get the formats configuration space.
22 * @ep: the endpoint to retrieve the space for.
24 * Return: A pointer to the formats configuration space.
29 struct acpi_nhlt_config *cfg = __acpi_nhlt_endpoint_config(ep); in acpi_nhlt_endpoint_fmtscfg() local
31 return (struct acpi_nhlt_formats_config *)((u8 *)(cfg + 1) + cfg->capabilities_size); in acpi_nhlt_endpoint_fmtscfg()
38 ((void *)((u8 *)(ep) + (ep)->length))
47 ((void *)((u8 *)((fmt) + 1) + (fmt)->config.capabilities_size))
[all …]
/linux/arch/sparc/kernel/
H A Dleon_pci_grpci1.c1 // SPDX-License-Identifier: GPL-2.0
32 /* Enable/Disable Debugging Configuration Space Access */
108 struct grpci1_priv *priv = dev->bus->sysdata; in grpci1_map_irq()
113 pin = ((pin - 1) + irq_group) & 0x3; in grpci1_map_irq()
115 return priv->irq_map[pin]; in grpci1_map_irq()
121 u32 *pci_conf, tmp, cfg; in grpci1_cfg_r32() local
124 return -EINVAL; in grpci1_cfg_r32()
134 cfg = REGLOAD(priv->regs->cfg_stat); in grpci1_cfg_r32()
135 REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23)); in grpci1_cfg_r32()
138 pci_conf = (u32 *) (priv->pci_conf | (devfn << 8) | (where & 0xfc)); in grpci1_cfg_r32()
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
36 /* set of registers with offsets different per-PHY */
139 /* struct qmp_phy_cfg - per-PHY initialization config */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
169 * struct qmp_phy - per-lane phy descriptor
172 * @cfg: phy specific configuration
173 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
[all …]
/linux/drivers/net/ethernet/netronome/nfp/crypto/
H A Dipsec.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
92 struct nfp_ipsec_aesgcm { /* AES-GCM-ESP fields */
135 unsigned int offset = nn->tlv_caps.mbox_off + NFP_NET_CFG_MBOX_SIMPLE_VAL; in nfp_net_ipsec_cfg()
136 struct nfp_ipsec_cfg_mssg *msg = (struct nfp_ipsec_cfg_mssg *)entry->msg; in nfp_net_ipsec_cfg()
143 msg_size = ARRAY_SIZE(msg->raw); in nfp_net_ipsec_cfg()
145 nn_writel(nn, offset + 4 * i, msg->raw[i]); in nfp_net_ipsec_cfg()
147 ret = nfp_net_mbox_reconfig(nn, entry->cmd); in nfp_net_ipsec_cfg()
155 msg->raw[i] = nn_readl(nn, offset + 4 * i); in nfp_net_ipsec_cfg()
159 switch (msg->rsp) { in nfp_net_ipsec_cfg()
163 return -EINVAL; in nfp_net_ipsec_cfg()
[all …]
/linux/drivers/tty/
H A Dmips_ejtag_fdc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
80 * and space becoming available in TX FIFO.
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
123 * @ports: Per-channel data.
124 * @waitqueue: Wait queue for waiting for TX data, or for space in TX
133 * @xmit_full: Indicates TX FIFO is full, we're waiting for space
488 u32 cfg; mips_ejtag_fdc_put() local
561 unsigned int stat, channel, data, cfg, i, flipped; mips_ejtag_fdc_handle() local
891 unsigned int cfg, tx_fifo; mips_ejtag_fdc_tty_probe() local
1051 unsigned int cfg; mips_ejtag_fdc_tty_cpu_down() local
1074 unsigned int cfg; mips_ejtag_fdc_tty_cpu_up() local
[all...]
/linux/drivers/scsi/cxlflash/
H A Dvlun.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 * marshal_virt_to_resize() - translate uvirtual to resize structure
34 resize->hdr = virt->hdr; in marshal_virt_to_resize()
35 resize->context_id = virt->context_id; in marshal_virt_to_resize()
36 resize->rsrc_handle = virt->rsrc_handle; in marshal_virt_to_resize()
37 resize->req_size = virt->lun_size; in marshal_virt_to_resize()
38 resize->last_lba = virt->last_lba; in marshal_virt_to_resize()
42 * marshal_clone_to_rele() - translate clone to release structure
49 release->hdr = clone->hdr; in marshal_clone_to_rele()
50 release->context_id = clone->context_id_dst; in marshal_clone_to_rele()
[all …]
/linux/drivers/virtio/
H A Dvirtio_pci_modern_dev.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * vp_modern_map_capability - map a part of virtio pci capability
10 * @mdev: the modern virtio-pci device
26 struct pci_dev *dev = mdev->pci_dev; in vp_modern_map_capability()
40 if (bar >= PCI_STD_NUM_BARS || !(mdev->modern_bars & (1 << bar))) { in vp_modern_map_capability()
41 dev_err(&dev->dev, in vp_modern_map_capability()
47 dev_err(&dev->dev, in vp_modern_map_capability()
53 if (length - start < minlen) { in vp_modern_map_capability()
54 dev_err(&dev->dev, in vp_modern_map_capability()
60 length -= start; in vp_modern_map_capability()
[all …]
/linux/drivers/net/ethernet/google/gve/
H A Dgve_tx.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
20 iowrite32be(val, &priv->db_bar2[be32_to_cpu(q_resources->db_index)]); in gve_tx_put_doorbell()
26 struct gve_tx_ring *tx = &priv->tx[tx_qid]; in gve_xdp_tx_flush()
28 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xdp_tx_flush()
35 * gve_tx_fifo_* manages the Registered Segment as a FIFO - clients must
41 fifo->base = vmap(fifo->qpl->pages, fifo->qpl->num_entries, VM_MAP, in gve_tx_fifo_init()
43 if (unlikely(!fifo->base)) { in gve_tx_fifo_init()
44 netif_err(priv, drv, priv->dev, "Failed to vmap fifo, qpl_id = %d\n", in gve_tx_fifo_init()
45 fifo->qpl->id); in gve_tx_fifo_init()
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
19 - items:
[all …]
H A Dxgene-pci.txt1 * AppliedMicro X-Gene PCIe interface
4 - device_type: set to "pci"
5 - compatible: should contain "apm,xgene-pcie" to identify the core.
6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
9 - reg-names: Must include the following entries:
11 "cfg": PCIe configuration space registers.
12 - #address-cells: set to <3>
13 - #size-cells: set to <2>
14 - ranges: ranges for the outbound memory, I/O regions.
[all …]
H A Dqcom,pcie-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sm8250
25 reg-names:
28 - const: parf # Qualcomm specific registers
29 - const: dbi # DesignWare PCIe registers
[all …]
/linux/drivers/vdpa/octeon_ep/
H A Doctep_vdpa_hw.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #define MBOX_RSP_TO_ERR(val) (-(((val) & MBOX_RC_MASK) >> 2))
53 return (struct octep_mbox __iomem *)(oct_hw->dev_cfg + MBOX_OFFSET); in octep_get_mbox()
60 return readx_poll_timeout(ioread32, &mbox->sts, val, MBOX_AVAIL(val), 10, in octep_wait_for_mbox_avail()
68 return readx_poll_timeout(ioread32, &mbox->sts, val, MBOX_RSP(val), 10, in octep_wait_for_mbox_rsp()
74 iowrite16(id, &mbox->hdr.id); in octep_write_hdr()
75 iowrite16(sig, &mbox->hd in octep_write_hdr()
301 struct virtio_pci_common_cfg __iomem *cfg = oct_hw->common_cfg; octep_set_vq_address() local
331 struct virtio_pci_common_cfg __iomem *cfg = oct_hw->common_cfg; octep_set_vq_num() local
339 struct virtio_pci_common_cfg __iomem *cfg = oct_hw->common_cfg; octep_set_vq_ready() local
347 struct virtio_pci_common_cfg __iomem *cfg = oct_hw->common_cfg; octep_get_vq_ready() local
[all...]
/linux/drivers/pci/controller/
H A Dpci-loongson.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pci-acpi.h>
13 #include <linux/pci-ecam.h>
58 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in bridge_class_quirk()
70 * The address space consumed by these devices is outside the in system_bus_quirk()
73 pdev->mmio_always_on = 1; in system_bus_quirk()
74 pdev->non_compliant_bars = 1; in system_bus_quirk()
93 struct pci_bus *bus = pdev->bus; in loongson_set_min_mrrs_quirk()
109 bridge = bus->self; in loongson_set_min_mrrs_quirk()
110 bus = bus->parent; in loongson_set_min_mrrs_quirk()
[all …]
/linux/arch/powerpc/kernel/
H A Deeh.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2001-2012 IBM Corporation.
32 #include <asm/ppc-pci.h>
34 #include <asm/pte-walk.h>
40 * usual PCI framework, except by check-stopping the CPU. Systems
41 * that are designed for high-availability/reliability cannot afford
43 * An EEH-capable bridge operates by converting a detected error
44 * into a "slot freeze", taking the PCI adapter off-line, making
50 * vibration, humidity, radioactivity or plain-old failed hardware.
55 * device to bus-master data to a memory address that is not
[all …]
/linux/drivers/gpu/drm/i915/gvt/
H A Dcfg_space.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
45 /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one
46 * byte) byte by byte in standard pci configuration space. (not the full
53 [PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,
59 * vgpu_pci_cfg_mem_write - write virtual cfg space memory
65 * Use this function to write virtual cfg space memory.
66 * For standard cfg space, only RW bits can be changed,
93 /* For other configuration space directly copy as it is. */ in vgpu_pci_cfg_mem_write()
95 memcpy(cfg_base + off + i, src + i, bytes - i); in vgpu_pci_cfg_mem_write()
97 if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) { in vgpu_pci_cfg_mem_write()
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c1 // SPDX-License-Identifier: GPL-2.0-only
67 u64 cfg; in xcv_init_hw() local
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
71 cfg &= ~DLL_RESET; in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
76 cfg &= ~CLK_RESET; in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
81 /* Configure DLL - enable or bypass in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
[all …]
/linux/arch/powerpc/platforms/pasemi/
H A Ddma_lib.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
43 /* pasemi_read_iob_reg - read IOB register
44 * @reg: Register to read (offset into PCI CFG space)
52 /* pasemi_write_iob_reg - write IOB register
53 * @reg: Register to write to (offset into PCI CFG space)
62 /* pasemi_read_mac_reg - read MAC register
64 * @reg: Register to read (offset into PCI CFG space)
72 /* pasemi_write_mac_reg - write MAC register
74 * @reg: Register to write to (offset into PCI CFG space)
[all …]
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_pcie_mac.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2021-2022, Intel Corporation.
20 #include <linux/io-64-nonatomic-lo-hi.h>
82 static int t7xx_pcie_mac_atr_cfg(struct t7xx_pci_dev *t7xx_dev, struct t7xx_atr_config *cfg) in t7xx_pcie_mac_atr_cfg() argument
84 struct device *dev = &t7xx_dev->pdev->dev; in t7xx_pcie_mac_atr_cfg()
90 if (cfg->transparent) { in t7xx_pcie_mac_atr_cfg()
94 if (cfg->src_addr & (cfg->size - 1)) { in t7xx_pcie_mac_atr_cfg()
96 return -EINVAL; in t7xx_pcie_mac_atr_cfg()
99 if (cfg->trsl_addr & (cfg->size - 1)) { in t7xx_pcie_mac_atr_cfg()
101 cfg->trsl_addr, cfg->size - 1); in t7xx_pcie_mac_atr_cfg()
[all …]
/linux/drivers/clk/xilinx/
H A Dxlnx_vcu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
11 #include <linux/clk-provider.h>
16 #include <linux/mfd/syscon/xlnx-vcu.h>
22 #include <dt-bindings/clock/xlnx-vcu.h>
50 * struct xvcu_device - Xilinx VCU init device structure
81 * struct xvcu_pll_cfg - Helper data
203 * xvcu_read - Read from the VCU register space
204 * @iomem: vcu reg space base address
216 * xvcu_write - Write to the VCU register space
[all …]
/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_mr.c15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
54 struct hns_roce_ida *mtpt_ida = &hr_dev->mr_table.mtpt_ida; in alloc_mr_key()
55 struct ib_device *ibdev = &hr_dev->ib_dev; in alloc_mr_key()
60 id = ida_alloc_range(&mtpt_ida->ida, mtpt_ida->min, mtpt_ida->max, in alloc_mr_key()
64 return -ENOMEM; in alloc_mr_key()
67 mr->key = hw_index_to_key(id); /* MR key */ in alloc_mr_key()
69 err = hns_roce_table_get(hr_dev, &hr_dev->mr_table.mtpt_table, in alloc_mr_key()
78 ida_free(&mtpt_ida->ida, id); in alloc_mr_key()
84 unsigned long obj = key_to_hw_index(mr->key); in free_mr_key()
[all …]
/linux/drivers/vdpa/ifcvf/
H A Difcvf_base.c1 // SPDX-License-Identifier: GPL-2.0-only
15 struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg; in ifcvf_set_vq_vector() local
17 vp_iowrite16(qid, &cfg->queue_select); in ifcvf_set_vq_vector()
18 vp_iowrite16(vector, &cfg->queue_msix_vector); in ifcvf_set_vq_vector()
20 return vp_ioread16(&cfg->queue_msix_vector); in ifcvf_set_vq_vector()
25 struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg; in ifcvf_set_config_vector() local
27 vp_iowrite16(vector, &cfg->msix_config); in ifcvf_set_config_vector()
29 return vp_ioread16(&cfg->msix_config); in ifcvf_set_config_vector()
38 length = le32_to_cpu(cap->length); in get_cap_addr()
39 offset = le32_to_cpu(cap->offset); in get_cap_addr()
[all …]
/linux/drivers/hwtracing/coresight/
H A Dcoresight-cfg-afdo.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "coresight-config.h"
11 #include "coresight-etm4x-cfg.h"
12 #include "coresight-cfg-preload.h"
44 /* strobe window counter 0 - reload from param 0 */
62 /* strobe period counter 1 - reload from param 1 */
93 /* view-inst */
128 * experimentation with mark / space ratios for various workloads
145 "Supplied presets allow experimentation with mark-space ratio for various loads\n",

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