| /linux/drivers/crypto/inside-secure/ |
| H A D | safexcel_ring.c | 14 struct safexcel_desc_ring *cdr, in safexcel_init_ring_descriptors() argument
22 cdr->offset = priv->config.cd_offset; in safexcel_init_ring_descriptors()
23 cdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
24 cdr->offset * EIP197_DEFAULT_RING_SIZE, in safexcel_init_ring_descriptors()
25 &cdr->base_dma, GFP_KERNEL); in safexcel_init_ring_descriptors()
26 if (!cdr->base) in safexcel_init_ring_descriptors()
28 cdr->write = cdr->base; in safexcel_init_ring_descriptors()
29 cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); in safexcel_init_ring_descriptors()
30 cdr->read = cdr->base; in safexcel_init_ring_descriptors()
33 cdr->shoffset = priv->config.cdsh_offset; in safexcel_init_ring_descriptors()
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| H A D | safexcel.c | 512 writel(lower_32_bits(priv->ring[i].cdr.base_dma), in safexcel_hw_setup_cdesc_rings()
514 writel(upper_32_bits(priv->ring[i].cdr.base_dma), in safexcel_hw_setup_cdesc_rings()
893 /* let the CDR know we have pending descriptors */ in safexcel_dequeue()
964 cdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].cdr); in safexcel_complete()
1006 safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr); in safexcel_invalidate_cache()
1623 &priv->ring[i].cdr, in safexcel_probe_generic()
1721 /* Reset the CDR base address */ in safexcel_hw_reset_rings()
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| /linux/drivers/net/can/sja1000/ |
| H A D | sja1000_isa.c | 35 static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; variable
56 module_param_array(cdr, byte, NULL, 0444);
57 MODULE_PARM_DESC(cdr, "Clock divider register "
190 if (cdr[idx] != 0xff) in sja1000_isa_probe()
191 priv->cdr = cdr[idx]; in sja1000_isa_probe()
192 else if (cdr[0] != 0xff) in sja1000_isa_probe()
193 priv->cdr = cdr[0]; in sja1000_isa_probe()
195 priv->cdr = CDR_DEFAULT; in sja1000_isa_probe()
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| H A D | sja1000_platform.c | 118 priv->cdr = pdata->cdr; in sp_populate()
186 priv->cdr |= divider / 2 - 1; in sp_populate_of()
188 priv->cdr |= CDR_CLKOUT_MASK; in sp_populate_of()
190 priv->cdr |= CDR_CLK_OFF; /* default */ in sp_populate_of()
194 priv->cdr |= CDR_CBP; /* default */ in sp_populate_of()
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| H A D | plx_pci.c | 79 * In the CDR register, you should set CBP to 1.
156 u8 cdr; /* clock divider register */ member
691 priv->cdr = ci->cdr; in plx_pci_add_card()
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| H A D | ems_pcmcia.c | 48 * In the CDR register, you should set CBP to 1.
218 priv->cdr = EMS_PCMCIA_CDR; in ems_pcmcia_add_card()
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| H A D | kvaser_pci.c | 63 * In the CDR register, you should set CBP to 1.
249 priv->cdr = KVASER_PCI_CDR; in kvaser_pci_add_chan()
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| H A D | peak_pcmcia.c | 122 * In the CDR register, you should set CBP to 1.
561 priv->cdr = PCC_CDR; in pcan_add_channels()
565 priv->cdr |= CDR_CLK_OFF; in pcan_add_channels()
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| H A D | ems_pci.c | 84 /* In the CDR register, you should set CBP to 1.
374 priv->cdr = EMS_PCI_CDR; in ems_pci_add_card()
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| /linux/arch/mips/cavium-octeon/executive/ |
| H A D | cvmx-helper-errata.c | 43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
45 * CDR for the specified QLM.
47 * @qlm: QLM to disable 2nd order CDR for.
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | amd-xgbe.txt | 46 - amd,serdes-cdr-rate: CDR rate speed selection
71 amd,serdes-cdr-rate = <2>, <2>, <7>;
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| H A D | cortina.txt | 7 devices, equipped with clock and data recovery (CDR) circuits. These
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| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | platform.c | 295 /* RX CDR present, bypass supported */ in apply_rx_cdr()
299 /* Power class <= 3, ignore config & turn RX CDR on */ in apply_rx_cdr()
321 /* Expand cdr setting to all 4 lanes */ in apply_rx_cdr()
329 /* Preserve current TX CDR status */ in apply_rx_cdr()
346 /* TX CDR present, bypass supported */ in apply_tx_cdr()
350 /* Power class <= 3, ignore config & turn TX CDR on */ in apply_tx_cdr()
373 /* Expand cdr setting to all 4 lanes */ in apply_tx_cdr()
380 /* Preserve current/determined RX CDR status */ in apply_tx_cdr()
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| /linux/arch/arm64/boot/dts/amd/ |
| H A D | amd-seattle-xgbe-b.dtsi | 49 amd,serdes-cdr-rate = <2>, <2>, <7>;
75 amd,serdes-cdr-rate = <2>, <2>, <7>;
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | parade-ps8622.c | 110 * [3:2] CDR tune wait cycle before measure for fine tune in ps8622_send_config()
127 /* 2.7G CDR settings: NOF=40LSB for HBR CDR setting */ in ps8622_send_config()
142 /* 1.62G CDR settings: [5:2]NOF=64LSB [1:0]DCO scale is 2/5 */ in ps8622_send_config()
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| /linux/include/linux/can/platform/ |
| H A D | sja1000.h | 33 u8 cdr; /* clock divider register */ member
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| /linux/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 301 pr_debug("XGBE: CDR centered, DLPF: %4d,%d,%d.\n", in netcp_xgbe_serdes_reset_cdr()
341 /* if no lock, then reset CDR */ in netcp_xgbe_check_link_status()
361 /* Lost the block lock, reset CDR if it is in netcp_xgbe_check_link_status()
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| /linux/drivers/net/phy/ |
| H A D | cortina.c | 97 MODULE_DESCRIPTION("Cortina EDC CDR 10G Ethernet PHY driver");
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| /linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | ti,ds90ub960.yaml | 90 ti,cdr-mode:
96 FPD-Link CDR Mode. This should reflect the hardware and the
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| /linux/drivers/scsi/mvsas/ |
| H A D | mv_defs.h | 281 PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
282 PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
283 PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
284 PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
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| H A D | mv_64xx.h | 98 VSR_PHY_MODE6 = 0x06, /* CDR */
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| /linux/drivers/mtd/devices/ |
| H A D | docg3.c | 234 int i, cdr, len4; in doc_read_data_area() local
239 cdr = len & 0x1; in doc_read_data_area()
240 len4 = len - cdr; in doc_read_data_area()
253 if (cdr) { in doc_read_data_area()
258 for (i = 0; i < cdr; i++) { in doc_read_data_area()
278 int i, cdr, len4; in doc_write_data_area() local
283 cdr = len & 0x3; in doc_write_data_area()
284 len4 = len - cdr; in doc_write_data_area()
294 for (i = 0; i < cdr; i++) { in doc_write_data_area()
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| /linux/drivers/net/ethernet/qualcomm/emac/ |
| H A D | emac-sgmii.c | 152 /* If we get a decoding error and CDR is not locked, then try in emac_sgmii_interrupt()
154 * clock with Clock and Data Recovery (CDR) to recover the in emac_sgmii_interrupt()
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| /linux/drivers/usb/host/ |
| H A D | bcma-hcd.c | 75 tmp = 0x1846b; /* set CDR to 0x11(fast) */ in bcma_hcd_4716wa()
77 tmp = 0x1046b; /* set CDR to 0x10(slow) */ in bcma_hcd_4716wa()
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| /linux/drivers/spi/ |
| H A D | spi-sun4i.c | 281 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) in sun4i_spi_transfer_one()
283 * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) in sun4i_spi_transfer_one()
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