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/linux/drivers/i2c/busses/
H A Di2c-qcom-cci.c105 struct cci;
113 struct cci *cci; member
123 struct cci { struct
135 struct cci *cci = dev; in cci_isr() argument
139 val = readl(cci->base + CCI_IRQ_STATUS_0); in cci_isr()
140 writel(val, cci->base + CCI_IRQ_CLEAR_0); in cci_isr()
141 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); in cci_isr()
144 complete(&cci->master[0].irq_complete); in cci_isr()
145 if (cci->master[1].master) in cci_isr()
146 complete(&cci->master[1].irq_complete); in cci_isr()
[all …]
/linux/lib/
H A Dcache_maint.c30 struct cache_coherency_ops_inst *cci = in __cache_coherency_ops_instance_free() local
32 kfree(cci); in __cache_coherency_ops_instance_free()
35 void cache_coherency_ops_instance_put(struct cache_coherency_ops_inst *cci) in cache_coherency_ops_instance_put() argument
37 kref_put(&cci->kref, __cache_coherency_ops_instance_free); in cache_coherency_ops_instance_put()
41 static int cache_inval_one(struct cache_coherency_ops_inst *cci, void *data) in cache_inval_one() argument
43 if (!cci->ops) in cache_inval_one()
46 return cci->ops->wbinv(cci, data); in cache_inval_one()
49 static int cache_inval_done_one(struct cache_coherency_ops_inst *cci) in cache_inval_done_one() argument
51 if (!cci->ops) in cache_inval_done_one()
54 if (!cci->ops->done) in cache_inval_done_one()
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
7 title: ARM CCI Cache Coherent Interconnect
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
35 Specifies base physical address of CCI control registers common to all
48 const: arm,cci-400-ctrl-if
71 - const: arm,cci-400-pmu,r0
[all …]
H A Dcci-control-port.yaml4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
19 cci-control-port:
33 cci-control-port = <&cci_control1>;
/linux/drivers/bus/
H A Darm-cci.c2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dmediatek,cci.yaml4 $id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
22 - mediatek,mt8183-cci
23 - mediatek,mt8186-cci
26 - mediatek,mt7988-cci
27 - const: mediatek,mt8183-cci
40 - const: cci
49 Phandle of the regulator for CCI that provides the supply voltage.
53 Phandle of the regulator for sram of CCI that provides the supply
[all …]
/linux/drivers/cache/
H A Dhisi_soc_hha.c46 struct cache_coherency_ops_inst cci; member
62 static int hisi_soc_hha_wbinv(struct cache_coherency_ops_inst *cci, in hisi_soc_hha_wbinv() argument
66 container_of(cci, struct hisi_soc_hha, cci); in hisi_soc_hha_wbinv()
105 static int hisi_soc_hha_done(struct cache_coherency_ops_inst *cci) in hisi_soc_hha_done() argument
108 container_of(cci, struct hisi_soc_hha, cci); in hisi_soc_hha_done()
129 struct hisi_soc_hha, cci); in hisi_soc_hha_probe()
150 ret = cache_coherency_ops_instance_register(&soc_hha->cci); in hisi_soc_hha_probe()
159 cache_coherency_ops_instance_put(&soc_hha->cci); in hisi_soc_hha_probe()
167 cache_coherency_ops_instance_unregister(&soc_hha->cci); in hisi_soc_hha_remove()
169 cache_coherency_ops_instance_put(&soc_hha->cci); in hisi_soc_hha_remove()
/linux/drivers/usb/typec/ucsi/
H A Dcros_ec_ucsi.c86 static int cros_ucsi_read_cci(struct ucsi *ucsi, u32 *cci) in cros_ucsi_read_cci() argument
88 return cros_ucsi_read(ucsi, UCSI_CCI, cci, sizeof(*cci)); in cros_ucsi_read_cci()
115 static int cros_ucsi_sync_control(struct ucsi *ucsi, u64 cmd, u32 *cci, in cros_ucsi_sync_control() argument
122 ret = ucsi_sync_control_common(ucsi, cmd, cci, data, size, msg_out, in cros_ucsi_sync_control()
126 /* EC may return -EBUSY if CCI.busy is set. in cros_ucsi_sync_control()
174 u32 cci; in cros_ucsi_work() local
176 if (cros_ucsi_read_cci(udata->ucsi, &cci)) in cros_ucsi_work()
179 ucsi_notify_common(udata->ucsi, cci); in cros_ucsi_work()
186 u32 cci; in cros_ucsi_write_timeout() local
189 if (cros_ucsi_read(udata->ucsi, UCSI_CCI, &cci, sizeof(cci))) { in cros_ucsi_write_timeout()
[all …]
H A Ducsi_acpi.c59 static int ucsi_acpi_read_cci(struct ucsi *ucsi, u32 *cci) in ucsi_acpi_read_cci() argument
63 memcpy(cci, ua->base + UCSI_CCI, sizeof(*cci)); in ucsi_acpi_read_cci()
68 static int ucsi_acpi_poll_cci(struct ucsi *ucsi, u32 *cci) in ucsi_acpi_poll_cci() argument
77 return ucsi_acpi_read_cci(ucsi, cci); in ucsi_acpi_poll_cci()
124 static int ucsi_gram_sync_control(struct ucsi *ucsi, u64 command, u32 *cci, in ucsi_gram_sync_control() argument
133 ret = ucsi_sync_control_common(ucsi, command, cci, val, len, in ucsi_gram_sync_control()
179 u32 cci; in ucsi_acpi_notify() local
182 ret = ua->ucsi->ops->read_cci(ua->ucsi, &cci); in ucsi_acpi_notify()
186 ucsi_notify_common(ua->ucsi, cci); in ucsi_acpi_notify()
H A Ducsi_yoga_c630.c50 static int yoga_c630_ucsi_read_cci(struct ucsi *ucsi, u32 *cci) in yoga_c630_ucsi_read_cci() argument
60 memcpy(cci, buf, sizeof(*cci)); in yoga_c630_ucsi_read_cci()
91 u32 *cci, in yoga_c630_ucsi_sync_control() argument
113 *cci = UCSI_CCI_COMMAND_COMPLETE | UCSI_SET_CCI_LENGTH(sizeof(alt)); in yoga_c630_ucsi_sync_control()
126 *cci = UCSI_CCI_COMMAND_COMPLETE; in yoga_c630_ucsi_sync_control()
130 ret = ucsi_sync_control_common(ucsi, command, cci, in yoga_c630_ucsi_sync_control()
193 u32 cci; in yoga_c630_ucsi_notify() local
204 ret = uec->ucsi->ops->read_cci(uec->ucsi, &cci); in yoga_c630_ucsi_notify()
208 ucsi_notify_common(uec->ucsi, cci); in yoga_c630_ucsi_notify()
H A Ducsi_ccg.c198 __le32 cci; member
231 * This spinlock protects op_data which includes CCI and MESSAGE_IN that
319 static int ccg_op_region_update(struct ucsi_ccg *uc, u32 cci) in ccg_op_region_update() argument
329 if (UCSI_CCI_LENGTH(cci)) { in ccg_op_region_update()
339 data->cci = cpu_to_le32(cci); in ccg_op_region_update()
340 if (UCSI_CCI_LENGTH(cci)) in ccg_op_region_update()
572 static int ucsi_ccg_read_cci(struct ucsi *ucsi, u32 *cci) in ucsi_ccg_read_cci() argument
577 *cci = uc->op_data.cci; in ucsi_ccg_read_cci()
600 * UCSI may read CCI instantly after async_control, in ucsi_ccg_async_control()
601 * clear CCI to avoid caller getting wrong data before we get CCI from ISR in ucsi_ccg_async_control()
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-cpus.dtsi62 cci-control-port = <&cci_control0>;
75 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
101 cci-control-port = <&cci_control0>;
114 cci-control-port = <&cci_control1>;
127 cci-control-port = <&cci_control1>;
140 cci-control-port = <&cci_control1>;
153 cci-control-port = <&cci_control1>;
H A Dexynos5420-cpus.dtsi63 cci-control-port = <&cci_control1>;
75 cci-control-port = <&cci_control1>;
87 cci-control-port = <&cci_control1>;
99 cci-control-port = <&cci_control1>;
111 cci-control-port = <&cci_control0>;
123 cci-control-port = <&cci_control0>;
135 cci-control-port = <&cci_control0>;
147 cci-control-port = <&cci_control0>;
H A Dexynos5260.dtsi67 cci-control-port = <&cci_control1>;
74 cci-control-port = <&cci_control1>;
81 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
95 cci-control-port = <&cci_control0>;
102 cci-control-port = <&cci_control0>;
355 cci: cci@10f00000 { label
356 compatible = "arm,cci-400";
363 compatible = "arm,cci-400-ctrl-if";
369 compatible = "arm,cci-400-ctrl-if";
/linux/include/linux/
H A Dcache_coherency.h22 int (*wbinv)(struct cache_coherency_ops_inst *cci,
24 int (*done)(struct cache_coherency_ops_inst *cci);
33 int cache_coherency_ops_instance_register(struct cache_coherency_ops_inst *cci);
34 void cache_coherency_ops_instance_unregister(struct cache_coherency_ops_inst *cci);
59 void cache_coherency_ops_instance_put(struct cache_coherency_ops_inst *cci);
H A Darm-cci.h3 * CCI cache coherent interconnect support
14 #include <asm/arm-cci.h>
/linux/drivers/perf/
H A Darm-cci.c2 // CCI Cache Coherent Interconnect PMU driver
6 #include <linux/arm-cci.h>
16 #define DRIVER_NAME "ARM-CCI PMU"
160 * Instead of an event id to monitor CCI cycles, a dedicated counter is
161 * provided. Use 0xff to represent CCI cycles and hope that no future revisions
172 * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
633 * Program the CCI PMU counters which have PERF_HES_ARCH set
739 * For all counters on the CCI-PMU, disable any 'enabled' counters,
778 * by the cci
824 dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); in pmu_request_irq()
[all …]
/linux/include/media/
H A Dv4l2-cci.h3 * MIPI Camera Control Interface (CCI) register access helpers.
18 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
38 * Private CCI register flags, for the use of drivers.
59 * cci_read() - Read a value from a single CCI register
72 * cci_write() - Write a value to a single CCI register
86 * a single CCI register
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi32 cci-control-port = <&cci_control2>;
40 cci-control-port = <&cci_control2>;
174 cci: cci@10390000 { label
175 compatible = "arm,cci-400";
182 compatible = "arm,cci-400-ctrl-if";
188 compatible = "arm,cci-400-ctrl-if";
194 compatible = "arm,cci-400-ctrl-if";
200 compatible = "arm,cci-400-pmu,r1";
/linux/arch/arm/mach-versatile/
H A Dplatsmp-vexpress.c28 * is to detect if the kernel can take over CCI ports in vexpress_smp_init_ops()
29 * control. Loop over possible CPUs and check if CCI in vexpress_smp_init_ops()
40 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); in vexpress_smp_init_ops()
/linux/Documentation/driver-api/media/
H A Dv4l2-cci.rst3 V4L2 CCI kAPI
5 .. kernel-doc:: include/media/v4l2-cci.h
/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_vf_dev.c13 * @cci: struct where the register offset pointer to be copied to
16 struct libie_ctlq_create_info *cci) in idpf_vf_ctlq_reg_init() argument
18 struct libie_ctlq_reg *tx_reg = &cci[LIBIE_CTLQ_TYPE_TX].reg; in idpf_vf_ctlq_reg_init()
19 struct libie_ctlq_reg *rx_reg = &cci[LIBIE_CTLQ_TYPE_RX].reg; in idpf_vf_ctlq_reg_init()
H A Didpf_dev.c14 * @cci: struct where the register offset pointer to be copied to
17 struct libie_ctlq_create_info *cci) in idpf_ctlq_reg_init() argument
19 struct libie_ctlq_reg *tx_reg = &cci[LIBIE_CTLQ_TYPE_TX].reg; in idpf_ctlq_reg_init()
20 struct libie_ctlq_reg *rx_reg = &cci[LIBIE_CTLQ_TYPE_RX].reg; in idpf_ctlq_reg_init()
/linux/arch/arm/boot/dts/allwinner/
H A Dsun9i-a80.dtsi70 cci-control-port = <&cci_control0>;
79 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
97 cci-control-port = <&cci_control0>;
106 cci-control-port = <&cci_control1>;
115 cci-control-port = <&cci_control1>;
124 cci-control-port = <&cci_control1>;
133 cci-control-port = <&cci_control1>;
551 cci: cci@1c90000 { label
552 compatible = "arm,cci-400";
[all …]
/linux/drivers/media/v4l2-core/
H A Dv4l2-cci.c3 * MIPI Camera Control Interface (CCI) register access helpers.
17 #include <media/v4l2-cci.h>
203 MODULE_DESCRIPTION("MIPI Camera Control Interface (CCI) support");

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