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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
H A Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
[all …]
H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-widt
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H A Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fq
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H A Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
H A Dt104xqds.dtsi4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
37 #address-cells = <2>;
38 #size-cells = <2>;
39 interrupt-parent = <&mpic>;
68 reserved-memory {
69 #address-cells = <2>;
70 #size-cells = <2>;
73 bman_fbpr: bman-fbpr {
77 qman_fqd: qman-fqd {
81 qman_pfdr: qman-pfdr {
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dinit.c1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
6 #include <linux/hwmon-sysfs.h>
54 struct mt7915_phy *phy = dev_get_drvdata(dev); in mt7915_thermal_temp_show() local
55 int i = to_sensor_dev_attr(attr)->index; in mt7915_thermal_temp_show()
60 temperature = mt7915_mcu_get_temperature(phy); in mt7915_thermal_temp_show()
68 phy->throttle_temp[i - 1] * 1000); in mt7915_thermal_temp_show()
70 return sprintf(buf, "%hhu\n", phy->throttle_state); in mt7915_thermal_temp_show()
72 return -EINVAL; in mt7915_thermal_temp_show()
80 struct mt7915_phy *phy = dev_get_drvdata(dev); in mt7915_thermal_temp_store() local
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dinit.c1 // SPDX-License-Identifier: ISC
3 * Copyright (C) 2022 MediaTek Inc.
57 dev = container_of(mphy->dev, struct mt7996_dev, mt76); in mt7996_led_set_config()
72 if (mphy->leds.al) in mt7996_led_set_config()
110 int i, nss = hweight8(dev->mphy.antenna_mask); in mt7996_init_txpower()
112 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); in mt7996_init_txpower()
115 for (i = 0; i < sband->n_channels; i++) { in mt7996_init_txpower()
116 struct ieee80211_channel *chan = &sband->channels[i]; in mt7996_init_txpower()
120 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, in mt7996_init_txpower()
125 chan->max_power = min_t(int, chan->max_reg_power, in mt7996_init_txpower()
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USBDP Combo PHY with Samsung IP block
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
21 "#phy-cells":
23 Cell allows setting the type of the PHY. Possible values are:
[all …]
H A Dqcom,msm8998-qmp-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB, MSM8998)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for USB-C on
19 - qcom,msm8998-qmp-usb3-phy
20 - qcom,qcm2290-qmp-usb3-phy
21 - qcom,sdm660-qmp-usb3-phy
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H A Dmediatek,mt8365-csi-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2023 MediaTek, BayLibre
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
11 - Julien Stephan <jstephan@baylibre.com>
12 - Andy Hsieh <andy.hsieh@mediatek.com>
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
17 Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
[all …]
/freebsd/sys/net80211/
H A Dieee80211_phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2008 Sam Leffler, Errno Consulting
30 * IEEE 802.11 PHY-related support.
79 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
80 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
81 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
82 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
83 [4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */
92 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1043a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
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H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
[all …]
H A Dfsl-ls1046a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2018-2019 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
20 emi1-slot1 = &ls1046mdio_s1;
21 emi1-slot2 = &ls1046mdio_s2;
22 emi1-slot4 = &ls1046mdio_s4;
27 qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
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H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/freebsd/sys/dev/isci/scil/
H A Dscic_sds_phy_registers.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
60 * @brief This file contains the macros used by the phy object to read/write
65 extern "C" {
75 * Macro to read the transport layer register associated with this phy
78 #define scu_transport_layer_read(phy, reg) \ argument
80 scic_sds_phy_get_controller(phy), \
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H A Dscif_sas_smp_phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
69 //* P U B L I C M E T H O D S
74 * @brief This routine constructs a smp phy object for an expander phy and insert
76 * @param[in] this_smp_phy The memory space to store a phy
77 * @param[in] owning_device The smp remote device that owns this smp phy.
78 * @param[in] expander_phy_id The expander phy id for this_smp_phy.
[all …]
H A Dsci_base_phy.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
61 * common to all phy object definitions.
65 extern "C" {
75 * @brief This enumeration depicts the standard states common to all phy
86 * This state indicates that the phy has successfully been stopped.
87 * In this state no new IO operations are permitted on this phy.
[all …]
H A Dscic_phy.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
61 * by an SCIC user on a phy (SAS or SATA) object.
65 extern "C" {
84 * supplied phy. This field may be set to SCI_INVALID_HANDLE
85 * if the phy is not currently contained in a port.
90 * This field specifies the maximum link rate for which this phy
[all …]
H A Dscic_sds_phy.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
65 extern "C" {
75 * This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
108 * Wait state for the PHY speed notification
128 * Wait state for the SATA PHY notification
133 * Wait for the SATA PHY speed notification
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp151c-mect1s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) Protonic Holland
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
21 stdout-path = "serial0:1500000n8";
33 v3v3: regulator-v3v3 {
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210phy.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
23 * Definitions for the PHY on the Atheros AR5210 parts.
26 /* PHY Registers */
27 #define AR_PHY_BASE 0x9800 /* PHY register base */
30 #define AR_PHY_FRCTL 0x9804 /* PHY frame control */
31 #define AR_PHY_TURBO_MODE 0x00000001 /* PHY turbo mode */
32 #define AR_PHY_TURBO_SHORT 0x00000002 /* PHY turbo short symbol */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211phy.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
23 * Definitions for the PHY on the Atheros AR5211/5311 chipset.
26 /* PHY registers */
27 #define AR_PHY_BASE 0x9800 /* PHY registers base address */
30 #define AR_PHY_TURBO 0x9804 /* PHY frame control register */
34 #define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */
36 #define AR_PHY_ACTIVE 0x981C /* PHY activation register */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-cc108.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2018 Xilinx, Inc.
6 * (C) Copyright 2007-2013 Michal Simek
7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
[all …]

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