Searched +full:bridge0 +full:- +full:2 (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Michal Simek <michal.simek@amd.com>14 - Introduction15 - Terminology16 - Sequence17 - FPGA Region18 - Supported Use Models[all …]
1 // SPDX-License-Identifier: GPL-2.0-only20 #define NR_CXL_HOST_BRIDGES 223 #define NR_CXL_ROOT_PORTS 224 #define NR_CXL_SWITCH_PORTS 254 if (&cxl_host_bridge[i]->dev == dev) in is_multi_bridge()64 if (&cxl_hb_single[i]->dev == dev) in is_single_bridge()79 [2] = {80 .handle = &host_bridge[2],81 .pnp.unique_id = "2",94 if (dev == &cxl_mem[i]->dev) in is_mock_dev()[all …]