Searched +full:bridge0 +full:- +full:2 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Michal Simek <michal.simek@amd.com>14 - Introduction15 - Terminology16 - Sequence17 - FPGA Region18 - Supported Use Models[all …]
1 // SPDX-License-Identifier: GPL-2.0-only21 #define NR_CXL_HOST_BRIDGES 224 #define NR_CXL_ROOT_PORTS 225 #define NR_CXL_SWITCH_PORTS 255 if (&cxl_host_bridge[i]->dev == dev) in is_multi_bridge() 65 if (&cxl_hb_single[i]->dev == dev) in is_single_bridge() 80 [2] [all...]
4 Contact: linux-cxl@vger.kernel.org14 Contact: linux-cxl@vger.kernel.org17 Memory Device Output Payload in the CXL-2.024 Contact: linux-cxl@vger.kernel.org34 Contact: linux-cxl@vger.kernel.org42 Contact: linux-cxl@vger.kernel.org46 Payload in the CXL-2.0 specification.52 Contact: linux-cxl@vger.kernel.org58 class-ids can be compared against a similar "qos_class"60 that the endpoints map their local memory-class to a[all …]