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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
57 bits<3> rd;
58 bits<3> rt;
59 bits<3> rs;
61 bits<16> Inst;
70 class ANDI_FM_MM16<bits<6> funct> {
71 bits<3> rd;
72 bits<3> rs;
[all …]
H A DMipsMSAInstrFormats.td30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
44 bits<5> ws;
45 bits<5> wd;
46 bits<4> m;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
57 bits<5> ws;
[all …]
H A DMicroMips32r6InstrFormats.td38 bits<10> offset;
40 bits<16> Inst;
46 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {
47 bits<3> rs;
48 bits<7> offset;
50 bits<16> Inst;
57 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
58 bits<5> rs;
60 bits<16> Inst;
68 bits<5> rt;
[all …]
H A DMipsInstrFormats.td26 class Format<bits<4> val> {
27 bits<4> Value = val;
74 field bits<32> Inst;
81 bits<6> Opcode = 0;
83 // Top 6 bits are the 'opcode' field
96 bits<4> FormBits = Form.Value;
111 field bits<32> SoftFail = 0;
151 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
155 bits<5> rd;
156 bits<5> rs;
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H A DMicroMipsDSPInstrFormats.td24 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
25 bits<5> rd;
26 bits<5> rs;
27 bits<5> rt;
36 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
37 bits<5> rt;
38 bits<5> rs;
47 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
48 bits<5> rt;
49 bits<5> rs;
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H A DMips32r6InstrFormats.td43 class OPGROUP<bits<6> Val> {
44 bits<6> Value = Val;
65 class OPCODE2<bits<2> Val> {
66 bits<2> Value = Val;
72 class OPCODE3<bits<3> Val> {
73 bits<3> Value = Val;
77 class OPCODE5<bits<5> Val> {
78 bits<5> Value = Val;
98 class OPCODE6<bits<6> Val> {
99 bits<6> Value = Val;
[all …]
H A DMipsDSPInstrFormats.td39 class Field6<bits<6> val> {
40 bits<6> V = val;
65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
79 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80 bits<5> rd;
81 bits<5> rs;
93 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td12 bits <5> Vu32;
14 bits <5> Rt32;
16 bits <5> Vdd32;
20 bits <7> Ii;
22 bits <5> Rs32;
24 bits <2> Pd4;
28 bits <5> Rss32;
30 bits <5> Rt32;
32 bits <2> Pd4;
36 bits <1
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td26 field bits<64> Inst;
30 bits<2> FlagOperandIdx = 0;
77 field bits<32> Word0;
79 bits<11> src0;
80 bits<1> src0_rel;
81 bits<11> src1;
82 bits<1> src1_rel;
83 bits<3> index_mode = 0;
84 bits<2> pred_sel;
85 bits<1> last;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
15 field bits<32> Inst;
16 field bits<32> SoftFail = 0;
28 bits<1> PPC970_First = 0;
29 bits<1> PPC970_Single = 0;
30 bits<1> PPC970_Cracked = 0;
31 bits<3> PPC970_Unit = 0;
41 bits<1> XFormMemOp = 0;
45 bits<1> Prefixed = 0;
49 // 32 bits t
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td16 field bits<16> Inst;
21 field bits<16> SoftFail = 0;
25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
28 bits<5> rs1;
29 bits<5> rs2;
38 // is responsible for setting the appropriate bits in the Inst field.
39 // The bits Inst{6-2} must be set for each instruction.
40 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
43 bits<10> imm;
44 bits<5> rd;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrFormats.td21 class Fmt1RI13_VI<bits<32> op, dag outs, dag ins, string opnstr,
24 bits<13> imm13;
25 bits<5> vd;
34 class Fmt2R_VV<bits<32> op, dag outs, dag ins, string opnstr,
37 bits<5> vj;
38 bits<5> vd;
46 class Fmt2R_VR<bits<32> op, dag outs, dag ins, string opnstr,
49 bits<5> rj;
50 bits<5> vd;
58 class Fmt2R_CV<bits<32> op, dag outs, dag ins, string opnstr,
[all …]
H A DLoongArchLASXInstrFormats.td21 class Fmt1RI13_XI<bits<32> op, dag outs, dag ins, string opnstr,
24 bits<13> imm13;
25 bits<5> xd;
34 class Fmt2R_XX<bits<32> op, dag outs, dag ins, string opnstr,
37 bits<5> xj;
38 bits<5> xd;
46 class Fmt2R_XR<bits<32> op, dag outs, dag ins, string opnstr,
49 bits<5> rj;
50 bits<5> xd;
58 class Fmt2R_CX<bits<32> op, dag outs, dag ins, string opnstr,
[all …]
H A DLoongArchInstrFormats.td22 field bits<32> Inst;
27 field bits<32> SoftFail = 0;
51 class Fmt2R<bits<32> op, dag outs, dag ins, string opnstr,
54 bits<5> rj;
55 bits<5> rd;
64 class Fmt3R<bits<32> op, dag outs, dag ins, string opnstr,
67 bits<5> rk;
68 bits<5> rj;
69 bits<5> rd;
79 class Fmt3RI2<bits<32> op, dag outs, dag ins, string opnstr,
[all …]
/freebsd/contrib/gdtoa/
H A Dstrtordd.c36 ULtodd(L, bits, exp, k) ULong *L; ULong *bits; Long exp; int k; in ULtodd() argument
38 ULtodd(ULong *L, ULong *bits, Long exp, int k)
50 L[_1] = (bits[1] >> 21 | bits[2] << 11) & (ULong)0xffffffffL;
51 L[_0] = (bits[2] >> 21) | (bits[3] << 11 & 0xfffff)
54 if (bits[1] &= 0x1fffff) {
55 i = hi0bits(bits[1]) - 11;
63 bits[1] = bits[1] << i | bits[0] >> (32-i);
64 bits[0] = bits[0] << i & (ULong)0xffffffffL;
67 else if (bits[0]) {
68 i = hi0bits(bits[0]) + 21;
[all …]
H A Dstrtopdd.c46 ULong bits[4]; local
60 rv = strtodg(s, sp, fpi, &exp, bits);
69 u->L[_1] = (bits[1] >> 21 | bits[2] << 11) & 0xffffffffL;
70 u->L[_0] = (bits[2] >> 21) | ((bits[3] << 11) & 0xfffff)
73 if (bits[1] &= 0x1fffff) {
74 i = hi0bits(bits[1]) - 11;
82 bits[1] = bits[1] << i | bits[0] >> (32-i);
83 bits[0] = bits[0] << i & 0xffffffffL;
86 else if (bits[0]) {
87 i = hi0bits(bits[0]) + 21;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dleds-lp55xx.txt41 clock-mode = /bits/ 8 <2>;
44 led-cur = /bits/ 8 <0x2f>;
45 max-cur = /bits/ 8 <0x5f>;
50 led-cur = /bits/ 8 <0x2f>;
51 max-cur = /bits/ 8 <0x5f>;
55 led-cur = /bits/ 8 <0x2f>;
56 max-cur = /bits/ 8 <0x5f>;
75 clock-mode = /bits/ 8 <1>;
79 led-cur = /bits/ 8 <0x14>;
80 max-cur = /bits/ 8 <0x20>;
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/freebsd/share/man/man3/
H A Dqmath.367 bits of precision after the binary radix point,
72 The number of bits available for the integral component is not explicitly
73 specified, and implicitly consumes the remaining available bits of the chosen Q
124 .Xr Q_PRECEQ 3 compare bits
134 .Ss Functions which manipulate the control/sign data bits
140 .Xr Q_GCRAW 3 raw control bits
141 .Xr Q_GCVAL 3 value of control bits
142 .Xr Q_SCVAL 3 set control bits
144 .Ss Functions which manipulate the combined integer/fractional data bits
147 .Xr Q_IFVALIMASK 3 value of integer bits
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td32 field bits<24> Inst;
33 field bits<24> SoftFail = 0;
40 field bits<16> Inst;
41 field bits<16> SoftFail = 0;
45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
48 bits<4> r;
49 bits<4> s;
50 bits<4> t;
60 class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
63 bits<4> r;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td9 class AddrMode<bits<5> val> {
10 bits<5> Value = val;
27 field bits<32> SoftFail = 0;
42 class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
45 field bits<32> Inst;
51 field bits<16> Inst;
57 class J<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern>
60 bits<26> offset;
68 class I_18_Z_L<bits<3> sop, string asm, dag outs, dag ins, list<dag> pattern>
70 bits<5> rz;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td71 bits<5> AccessBytes = 0;
76 bits<4> CCValues = 0;
81 bits<4> CompareZeroCCMask = 0;
172 // bits<4> Rn : register input or output for operand n
173 // bits<5> Vn : vector register input or output for operand n
174 // bits<m> In : immediate value of width m for operand n
175 // bits<4> Bn : base register for address operand n
176 // bits<m> Dn : displacement for address operand n
177 // bits<5> Vn : vector index for address operand n
178 // bits<4> Xn : index register for address operand n
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DBitVector.h32 /// ForwardIterator for the bits that are set.
92 Storage Bits; // Actual bits. variable
93 unsigned Size = 0; // Size of bitvector in bits.
106 WordRef = &b.Bits[Idx / BITWORD_SIZE]; in reference()
147 /// BitVector ctor - Creates a bitvector of specified number of bits. All
148 /// bits are initialized to the specified value.
150 : Bits(NumBitWords(s), 0 - (BitWord)t), Size(s) { in NumBitWords()
155 /// empty - Tests whether there are no bits in this bitvector.
158 /// size - Returns the number of bits in this bitvector.
161 /// count - Returns the number of bits which are set.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td12 field bits<32> Inst;
17 bits<2> op;
18 let Inst{31-30} = op; // Top two bits are the 'op' field
26 field bits<32> SoftFail = 0;
39 bits<3> op2;
40 bits<22> imm22;
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
51 bits<5> rd;
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
61 bits<
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-peripherals-opp.dtsi59 opp-hz = /bits/ 64 <12750000>;
66 opp-hz = /bits/ 64 <12750000>;
73 opp-hz = /bits/ 64 <12750000>;
80 opp-hz = /bits/ 64 <25500000>;
87 opp-hz = /bits/ 64 <25500000>;
94 opp-hz = /bits/ 64 <25500000>;
101 opp-hz = /bits/ 64 <27000000>;
108 opp-hz = /bits/ 64 <27000000>;
115 opp-hz = /bits/ 64 <27000000>;
122 opp-hz = /bits/ 64 <51000000>;
[all …]
H A Dtegra124-peripherals-opp.dtsi9 opp-hz = /bits/ 64 <12750000>;
15 opp-hz = /bits/ 64 <12750000>;
21 opp-hz = /bits/ 64 <12750000>;
27 opp-hz = /bits/ 64 <12750000>;
33 opp-hz = /bits/ 64 <20400000>;
39 opp-hz = /bits/ 64 <20400000>;
45 opp-hz = /bits/ 64 <20400000>;
51 opp-hz = /bits/ 64 <20400000>;
57 opp-hz = /bits/ 64 <40800000>;
63 opp-hz = /bits/ 64 <40800000>;
[all …]

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