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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
76 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
77 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
78 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
79 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
80 uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass
92 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
[all …]
/linux/sound/soc/codecs/
H A Dwm8990.c104 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
106 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
108 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
110 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
112 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
114 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
118 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
120 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
122 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
124 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
[all …]
H A Dwm8400.c140 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
142 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
144 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
146 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
148 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
150 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
154 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
156 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
158 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
160 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
[all …]
H A Dwm8991.c176 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3,
178 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
180 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
182 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5,
184 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
186 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
190 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4,
192 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
194 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
196 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6,
[all …]
H A Dtlv320aic3x.c331 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
336 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
341 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
346 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
351 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
356 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
362 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
369 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
376 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
431 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
[all …]
H A Dwm9712.c166 SOC_SINGLE("PCBeep Bypass Headphone Volume", AC97_PC_BEEP, 12, 7, 1),
167 SOC_SINGLE("PCBeep Bypass Speaker Volume", AC97_PC_BEEP, 8, 7, 1),
168 SOC_SINGLE("PCBeep Bypass Phone Volume", AC97_PC_BEEP, 4, 7, 1),
288 WM9712_HP_MIXER_CTRL("PCBeep Bypass Switch", HPL_MIXER, 5),
290 WM9712_HP_MIXER_CTRL("Phone Bypass Switch", HPL_MIXER, 3),
291 WM9712_HP_MIXER_CTRL("Line Bypass Switch", HPL_MIXER, 2),
298 WM9712_HP_MIXER_CTRL("PCBeep Bypass Switch", HPR_MIXER, 5),
300 WM9712_HP_MIXER_CTRL("Phone Bypass Switch", HPR_MIXER, 3),
301 WM9712_HP_MIXER_CTRL("Line Bypass Switch", HPR_MIXER, 2),
308 SOC_DAPM_SINGLE("PCBeep Bypass Switch", AC97_PC_BEEP, 11, 1, 1),
[all …]
H A Dadau1373.c602 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
603 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
604 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
605 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
626 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0),
627 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0),
628 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0),
629 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0),
635 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0),
636 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0),
[all …]
H A Dtlv320dac33.c465 "Bypass", "Mode 1", "Mode 7"
510 /* Analog bypass */
544 /* Analog bypass */
545 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
547 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
555 * For DAPM path, when only the anlog bypass path is enabled, and the
559 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
560 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
580 /* Analog bypass */
581 {"Analog Left Bypass", "Switch", "LINEL"},
[all …]
H A Disabelle.c414 SOC_SINGLE("ATX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
416 SOC_SINGLE("ATX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
418 SOC_SINGLE("ARX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
420 SOC_SINGLE("ARX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
422 SOC_SINGLE("ARX3 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
424 SOC_SINGLE("ARX4 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
426 SOC_SINGLE("ARX5 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
428 SOC_SINGLE("ARX6 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
430 SOC_SINGLE("VRX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
432 SOC_SINGLE("VRX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
[all …]
H A Dwm8971.c142 SOC_DOUBLE_R("Bypass Left Playback Volume", WM8971_LOUTM1,
144 SOC_DOUBLE_R("Bypass Right Playback Volume", WM8971_ROUTM1,
146 SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8971_MOUTM1,
194 SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_LOUTM1, 7, 1, 0),
196 SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_LOUTM2, 7, 1, 0),
202 SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_ROUTM1, 7, 1, 0),
204 SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_ROUTM2, 7, 1, 0),
210 SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_MOUTM1, 7, 1, 0),
212 SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_MOUTM2, 7, 1, 0),
286 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
[all …]
/linux/include/linux/
H A Dirqbypass.h3 * IRQ offload/bypass manager
18 * The IRQ bypass manager is a simple set of lists and callbacks that allows
20 * consumers (ex. virtualization hardware that allows IRQ bypass or offload)
32 * struct irq_bypass_producer - IRQ bypass producer definition
33 * @node: IRQ bypass manager private list management
41 * The IRQ bypass producer structure represents an interrupt source for
42 * participation in possible host bypass, for instance an interrupt vector
58 * struct irq_bypass_consumer - IRQ bypass consumer definition
59 * @node: IRQ bypass manager private list management
66 * The IRQ bypass consumer structure represents an interrupt sink for
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dsmsc,usb3503.yaml37 bypass-gpios:
40 GPIO for bypass.
41 Control signal to select between HUB MODE and BYPASS MODE.
57 Specifies initial mode. 1 for Hub mode, 2 for standby mode and 3 for bypass mode.
58 In bypass mode the downstream port 3 is connected to the upstream port with low
91 bypass-gpios: false
95 - bypass-gpios
138 bypass-gpios = <&gpx3 6 1>;
/linux/drivers/usb/misc/
H A Dusb3503.c49 struct gpio_desc *bypass; member
113 int rst, bypass, conn; in usb3503_switch_mode() local
119 bypass = 0; in usb3503_switch_mode()
124 bypass = 1; in usb3503_switch_mode()
130 bypass = 1; in usb3503_switch_mode()
143 if (hub->bypass) in usb3503_switch_mode()
144 gpiod_set_value_cansleep(hub->bypass, bypass); in usb3503_switch_mode()
261 hub->bypass = devm_gpiod_get_optional(dev, "bypass", GPIOD_OUT_HIGH); in usb3503_probe()
262 if (IS_ERR(hub->bypass)) { in usb3503_probe()
263 err = PTR_ERR(hub->bypass); in usb3503_probe()
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Dfrontend.json52 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
82 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
92 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
110 …e uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instr…
119 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
129 …nstruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
138 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Dfrontend.json52 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
82 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
92 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
110 …e uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instr…
119 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
129 …nstruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
138 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A Dfrontend.json52 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
82 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
92 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
110 …e uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instr…
119 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
129 …nstruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
138 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
[all …]
/linux/include/trace/events/
H A Dbcache.h124 TP_PROTO(struct bio *bio, bool hit, bool bypass),
125 TP_ARGS(bio, hit, bypass),
133 __field(bool, bypass )
142 __entry->bypass = bypass;
145 TP_printk("%d,%d %s %llu + %u hit %u bypass %u",
148 __entry->nr_sector, __entry->cache_hit, __entry->bypass)
153 bool writeback, bool bypass),
154 TP_ARGS(c, inode, bio, writeback, bypass),
163 __field(bool, bypass )
173 __entry->bypass = bypass;
[all …]
/linux/drivers/regulator/
H A Danatop-regulator.c30 bool bypass; member
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
100 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) in anatop_regmap_core_get_voltage_sel()
113 WARN_ON(!anatop_reg->bypass); in anatop_regmap_get_bypass()
115 WARN_ON(anatop_reg->bypass); in anatop_regmap_get_bypass()
117 *enable = anatop_reg->bypass; in anatop_regmap_get_bypass()
126 if (enable == anatop_reg->bypass) in anatop_regmap_set_bypass()
130 anatop_reg->bypass = enable; in anatop_regmap_set_bypass()
270 sreg->bypass = true; in anatop_regulator_probe()
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-ip.h32 struct cv1800_clk_regbit bypass; member
44 struct cv1800_clk_regbit bypass; member
52 struct cv1800_clk_regbit bypass; member
123 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
143 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
186 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
218 .bypass = CV1800_CLK_BIT(_bypass_reg, \
H A Dclk-cv18xx-ip.c309 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_round_rate()
336 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_recalc_rate()
347 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_set_rate()
357 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_get_parent()
368 return cv1800_clk_clearbit(&div->div.common, &div->bypass); in bypass_div_set_parent()
370 return cv1800_clk_setbit(&div->div.common, &div->bypass); in bypass_div_set_parent()
520 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_round_rate()
547 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_recalc_rate()
558 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_set_rate()
568 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_get_parent()
[all …]
/linux/virt/lib/
H A Dirqbypass.c3 * IRQ offload/bypass manager
14 * bypass.
23 MODULE_DESCRIPTION("IRQ bypass manager utility module");
78 * irq_bypass_register_producer - register IRQ bypass producer
129 * irq_bypass_unregister_producer - unregister IRQ bypass producer
173 * irq_bypass_register_consumer - register IRQ bypass consumer
225 * irq_bypass_unregister_consumer - unregister IRQ bypass consumer
/linux/drivers/clk/at91/
H A Dsckc.c122 bool bypass, in at91_clk_register_slow_osc() argument
148 if (bypass) in at91_clk_register_slow_osc()
378 bool bypass; in at91sam9x5_sckc_register() local
398 bypass = of_property_read_bool(child, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
402 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
411 &parent_data, 1200000, bypass, bits); in at91sam9x5_sckc_register()
479 bool bypass; in of_sam9x60_sckc_setup() local
496 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in of_sam9x60_sckc_setup()
498 &parent_data, 5000000, bypass, in of_sam9x60_sckc_setup()
/linux/drivers/clk/imx/
H A Dclk-sscg-pll.c75 int bypass; member
146 temp_setup->bypass = PLL_BYPASS1; in clk_sscg_divq_lookup()
220 temp_setup->bypass = PLL_BYPASS_NONE; in clk_sscg_divf1_lookup()
280 setup->bypass = PLL_BYPASS2; in clk_sscg_pll_find_setup()
365 /* set bypass here too since the parent might be the same */ in clk_sscg_pll_set_rate()
368 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); in clk_sscg_pll_set_rate()
405 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); in clk_sscg_pll_set_parent()
416 int bypass) in __clk_sscg_pll_determine_rate() argument
427 switch (bypass) { in __clk_sscg_pll_determine_rate()
443 rate, bypass); in __clk_sscg_pll_determine_rate()
/linux/drivers/clk/ti/
H A Dclkt_dpll.c175 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
178 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
179 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
188 * Each set bit in the mask corresponds to a bypass value equal in _omap2_dpll_is_in_bypass()
217 /* Reparent the struct clk in case the dpll is in bypass */ in omap2_init_dpll_parent()
231 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
233 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
235 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
248 /* Return bypass rate if DPLL is bypassed */ in omap2_get_dpll_rate()
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt5 (reference clock and bypass clock), with digital phase locked
36 and second entry bypass clock
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
79 ti,low-power-bypass;

12345678910>>...51