Searched full:bws (Results 1 – 9 of 9) sorted by relevance
/linux/Documentation/devicetree/bindings/clock/ti/ |
H A D | dra7-atl.txt | 6 ATL can maintain a clock averages to some desired frequency based on the bws/aws 42 - bws : Baseband word select signal selection 91 bws = <DRA7_ATL_WS_MCASP2_FSX>;
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/linux/drivers/clk/ti/ |
H A D | clk-dra7-atl.c | 47 u32 bws; /* Baseband Word Select Mux */ member 259 ret = of_property_read_u32(cfg_node, "bws", in of_dra7_atl_clk_probe() 260 &cdesc->bws); in of_dra7_atl_clk_probe() 266 cdesc->bws); in of_dra7_atl_clk_probe()
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dra7-evm-common.dtsi | 225 bws = <DRA7_ATL_WS_MCASP2_FSX>;
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H A D | dra72-evm-common.dtsi | 560 bws = <DRA7_ATL_WS_MCASP2_FSX>;
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/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | maxim,max9286.yaml | 58 the BWS pin, but may be overridden with this property. The value must
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/linux/drivers/gpu/drm/gma500/ |
H A D | cdv_intel_dp.c | 900 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; in cdv_intel_dp_mode_fixup() local 912 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup() 915 intel_dp->link_bw = bws[clock]; in cdv_intel_dp_mode_fixup() 929 intel_dp->link_bw = bws[max_clock]; in cdv_intel_dp_mode_fixup()
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/linux/Documentation/networking/device_drivers/ethernet/ti/ |
H A D | cpsw.rst | 172 // TX queues must be rated starting from 0, so set bws for tx0 and tx1 403 // TX queues must be rated starting from 0, so set bws for tx0 and tx1 for Eth0
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/linux/net/wireless/ |
H A D | reg.c | 1650 static const u32 bws[] = {0, 1, 2, 4, 5, 8, 10, 16, 20}; in __freq_reg_info() local 1652 int i = ARRAY_SIZE(bws) - 1; in __freq_reg_info() 1655 for (bw = MHZ_TO_KHZ(bws[i]); bw >= min_bw; bw = MHZ_TO_KHZ(bws[i--])) { in __freq_reg_info()
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/linux/drivers/media/i2c/ |
H A D | max9286.c | 1494 * will keep the default value selected by the BWS pin. in max9286_parse_dt()
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