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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra186.dtsi10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
79 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
123 clocks = <&bpmp TEGRA186_CLK_APE>,
124 <&bpmp TEGRA186_CLK_APB2AP
1907 bpmp: bpmp { global() label
[all...]
H A Dtegra194.dtsi10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
154 resets = <&bpmp TEGRA194_RESET_EQOS>;
173 resets = <&bpmp TEGRA194_RESET_GPCDMA>;
217 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA194_CLK_APB2AP
2849 bpmp: bpmp { global() label
[all...]
H A Dtegra234.dtsi11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
124 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
167 clocks = <&bpmp TEGRA234_CLK_APE>,
168 <&bpmp TEGRA234_CLK_APB2APE>;
170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
180 clocks = <&bpmp TEGRA234_CLK_AHUB>;
182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
195 clocks = <&bpmp TEGRA234_CLK_I2S1>,
196 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra186-display.yaml128 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
129 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
130 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
131 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
132 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
133 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
134 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
137 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
138 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
139 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
[all …]
H A Dnvidia,tegra20-dsi.yaml150 clocks = <&bpmp TEGRA186_CLK_DSI>,
151 <&bpmp TEGRA186_CLK_DSIA_LP>,
152 <&bpmp TEGRA186_CLK_PLLD>;
154 resets = <&bpmp TEGRA186_RESET_DSI>;
157 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
7 title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
14 The BPMP is a specific processor in Tegra chip, which is designed for
17 defines the resources that would be used by the BPMP firmware driver,
19 CPU and BPMP.
39 The BPMP implements some services which must be represented by
43 BPMP node.
45 Software can determine whether a child node of the BPMP node
49 provide configuration information regarding the BPMP itself, although
52 The BPMP firmwar
[all...]
H A Dnvidia,tegra186-bpmp.txt1 NVIDIA Tegra Boot and Power Management Processor (BPMP)
3 The BPMP is a specific processor in Tegra chip, which is designed for
6 defines the resources that would be used by the BPMP firmware driver,
8 and BPMP.
14 - "nvidia,tegra186-bpmp"
17 the IPC between CPU and BPMP is based on.
40 The BPMP implements some services which must be represented by separate nodes.
43 be nested directly inside the main BPMP node.
45 Software can determine whether a child node of the BPMP node represents a device
48 property may be used to provide configuration information regarding the BPMP
[all …]
H A Dnvidia,tegra210-bpmp.txt1 NVIDIA Tegra210 Boot and Power Management Processor (BPMP)
3 The Boot and Power Management Processor (BPMP) is a co-processor found
8 be used by the BPMP T210 firmware driver, which can create the
9 interprocessor communication (IPC) between the CPU and BPMP.
15 - "nvidia,tegra210-bpmp"
24 offloaded to bpmp.
28 bpmp@70016000 {
29 compatible = "nvidia,tegra210-bpmp";
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dnvidia,tegra186-bpmp-i2c.txt1 NVIDIA Tegra186 BPMP I2C controller
3 In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
5 running on other CPUs must perform IPC to the BPMP in order to execute
9 The BPMP I2C node must be located directly inside the main BPMP node. See
10 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
19 - "nvidia,tegra186-bpmp-i2c".
26 - nvidia,bpmp-bus-id:
29 BPMP firmware.
33 bpmp {
37 compatible = "nvidia,tegra186-bpmp-i2c";
[all …]
H A Dnvidia,tegra186-bpmp-i2c.yaml4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
7 title: NVIDIA Tegra186 (and later) BPMP I2C controller
14 In Tegra186 and later, the BPMP (Boot and Power Management Processor)
17 the BPMP in order to execute transactions on that I2C bus. This
20 The BPMP I2C node must be located directly inside the main BPMP node.
21 See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
28 const: nvidia,tegra186-bpmp-i2c
30 nvidia,bpmp-bus-id:
33 as defined by the BPMP firmware.
44 - nvidia,bpmp-bus-id
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra186-bpmp-thermal.txt1 NVIDIA Tegra186 BPMP thermal sensor
3 In Tegra186, the BPMP (Boot and Power Management Processor) implements an
6 exposed by BPMP.
8 The BPMP thermal node must be located directly inside the main BPMP node. See
9 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
18 - "nvidia,tegra186-bpmp-thermal"
19 - "nvidia,tegra194-bpmp-thermal"
26 bpmp {
30 compatible = "nvidia,tegra186-bpmp-thermal";
H A Dnvidia,tegra186-bpmp-thermal.yaml4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml#
7 title: NVIDIA Tegra186 (and later) BPMP thermal sensor
14 In Tegra186, the BPMP (Boot and Power Management Processor) implements
17 sensor that is exposed by BPMP.
19 The BPMP thermal node must be located directly inside the main BPMP
20 node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the
21 BPMP binding.
28 - nvidia,tegra186-bpmp-thermal
29 - nvidia,tegra194-bpmp-thermal
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dnvidia,tegra234-mgbe.yaml124 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
125 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
126 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
127 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
128 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
129 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
130 <&bpmp TEGRA234_CLK_MGBE0_TX>,
131 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
132 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
133 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dnvidia,tegra234-xusb.yaml133 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
134 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
135 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
136 <&bpmp TEGRA234_CLK_XUSB_SS>,
137 <&bpmp TEGRA234_CLK_CLK_M>,
138 <&bpmp TEGRA234_CLK_XUSB_FS>,
139 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
140 <&bpmp TEGRA234_CLK_CLK_M>,
141 <&bpmp TEGRA234_CLK_PLLE>;
151 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
[all …]
H A Dnvidia,tegra186-xusb.yaml145 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
146 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
147 <&bpmp TEGRA186_CLK_XUSB_SS>,
148 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
149 <&bpmp TEGRA186_CLK_CLK_M>,
150 <&bpmp TEGRA186_CLK_XUSB_FS>,
151 <&bpmp TEGRA186_CLK_PLLU>,
152 <&bpmp TEGRA186_CLK_CLK_M>,
153 <&bpmp TEGRA186_CLK_PLLE>;
157 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
[all …]
H A Dnvidia,tegra194-xusb.yaml148 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
149 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
150 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
151 <&bpmp TEGRA194_CLK_XUSB_SS>,
152 <&bpmp TEGRA194_CLK_CLK_M>,
153 <&bpmp TEGRA194_CLK_XUSB_FS>,
154 <&bpmp TEGRA194_CLK_UTMIPLL>,
155 <&bpmp TEGRA194_CLK_CLK_M>,
156 <&bpmp TEGRA194_CLK_PLLE>;
166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dnvidia,tegra194-pcie-ep.yaml116 nvidia,bpmp:
119 Must contain a pair of phandles to BPMP controller node followed by
147 - description: phandle to BPMP controller node
204 - nvidia,bpmp
229 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
232 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
233 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
236 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
240 nvidia,bpmp = <&bpmp 5>;
278 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
[all …]
H A Dnvidia,tegra194-pcie.yaml115 nvidia,bpmp:
118 Must contain a pair of phandles to BPMP controller node followed by
146 - description: phandle to BPMP controller node
251 - nvidia,bpmp
267 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
283 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
286 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
287 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
298 nvidia,bpmp = <&bpmp 0>;
333 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
[all …]
H A Dnvidia,tegra194-pcie.txt48 - nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
146 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
161 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
164 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
165 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
176 nvidia,bpmp = <&bpmp 0>;
202 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
216 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
219 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
220 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpu/
H A Dnvidia,gk20a.txt87 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
88 <&bpmp TEGRA186_CLK_GPU>;
90 resets = <&bpmp TEGRA186_RESET_GPU>;
92 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
105 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
106 <&bpmp TEGRA194_CLK_GPU_PWR>,
107 <&bpmp TEGRA194_CLK_FUSE>;
109 resets = <&bpmp TEGRA194_RESET_GPU>;
113 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra-ccplex-cluster.yaml31 nvidia,bpmp:
34 Specifies the BPMP node that needs to be queried to get
42 - nvidia,bpmp
49 nvidia,bpmp = <&bpmp>;
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra186-mc.yaml65 controller on NVIDIA Tegra186 and later is performed on the BPMP. This
97 nvidia,bpmp:
100 phandle of the node representing the BPMP
139 - nvidia,bpmp
268 clocks = <&bpmp TEGRA186_CLK_EMC>;
273 nvidia,bpmp = <&bpmp>;
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dnvidia,tegra194-ccplex.yaml27 nvidia,bpmp:
30 Specifies the bpmp node that needs to be queried to get
39 nvidia,bpmp = <&bpmp>;
/freebsd/sys/contrib/device-tree/Bindings/gpu/host1x/
H A Dnvidia,tegra234-nvdec.yaml134 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
135 <&bpmp TEGRA234_CLK_FUSE>,
136 <&bpmp TEGRA234_CLK_TSEC_PKA>;
138 resets = <&bpmp TEGRA234_RESET_NVDEC>;
140 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
H A Dnvidia,tegra210-nvjpg.yaml84 clocks = <&bpmp TEGRA186_CLK_NVJPG>;
86 resets = <&bpmp TEGRA186_RESET_NVJPG>;
89 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;

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