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/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dti,j784s4-bist.yaml5 $id: http://devicetree.org/schemas/soc/ti/ti,j784s4-bist.yaml#
8 title: Texas Instruments K3 BIST
17 The BIST (Built-In Self Test) module is an IP block present in K3 devices
18 that support triggering of BIST tests, both PBIST (Memory BIST) and LBIST
19 (Logic BIST) on a core. Both tests are destructive in nature. At boot, BIST
24 const: ti,j784s4-bist
55 compatible = "ti,j784s4-bist";
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_interface.h151 /** Serdes BIST pattern */
487 * Enable BIST required overrides
495 * Disable BIST required overrides
608 * SERDES BIST pattern selection
609 * Selects the BIST pattern to be used
619 * SERDES BIST TX Enable
620 * Enables/disables TX BIST per lane
624 * @param enable Enable or disable TX BIST
628 * SERDES BIST TX single bit error injection
629 * Injects single bit error during a TX BIST
[all …]
H A Dal_hal_serdes_hssp_internal_regs.h161 /* Receive lane BIST enable. Active High */
165 /* TX lane BIST enable. Active High */
170 * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
177 * RX BIST error count overflow indicator. Indicates an overflow in the number
185 * RX BIST locked indicator 0 - Indicates BIST is not word locked and error
186 * comparisons have not begun yet 1 - Indicates BIST is word locked and error
193 * RX BIST error count word. Indicates the number of byte errors identified
578 * Selects the transmit BIST mode:
H A Dal_hal_serdes_internal_regs.h162 /* Receive lane BIST enable. Active High */
166 /* TX lane BIST enable. Active High */
171 * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
178 * RX BIST error count overflow indicator. Indicates an overflow in the number
186 * RX BIST locked indicator 0 - Indicates BIST is not word locked and error
187 * comparisons have not begun yet 1 - Indicates BIST is word locked and error
194 * RX BIST error count word. Indicates the number of byte errors identified
579 * Selects the transmit BIST mode:
/freebsd/sys/dev/mii/
H A Dnsphyterreg.h155 #define PHYCRTL_MP_PSR_15 0x0800 /* BIST sequence select */
156 #define PHYCTRL_MP_BIST_STAT 0x0400 /* BIST passed */
157 #define PHYCTRL_MP_BIST_START 0x0200 /* start BIST */
/freebsd/sys/dev/sfxge/common/
H A Defx_check.h233 # error "PHY_BIST is obsolete (replaced by BIST)."
339 /* Support BIST */
343 # error "BIST requires SIENA or HUNTINGTON or MEDFORD or MEDFORD2"
H A Def10_phy.c664 * MCDI_CTL_SDU_LEN_MAX_V1 is large enough cover all BIST results,
774 /* There is no way to stop BIST on EF10. */ in ef10_bist_stop()
/freebsd/sys/dev/cas/
H A Dif_casreg.h57 #define CAS_BIM_RAM_BIST 0x1030 /* BIM RAM BIST control/status */
150 #define CAS_BIM_RAM_BIST_START 0x00000001 /* Start BIST on read buffer. */
225 #define CAS_TX_RAM_BIST 0x211c /* TX RAM BIST control/status */
273 #define CAS_TX_RAM_BIST_START 0x00000001 /* Start RAM BIST process. */
279 #define CAS_TX_RAM_BIST_SM 0x000001c0 /* RAM BIST state machine */
306 #define CAS_RX_BIST 0x4060 /* RX BIST */
442 #define CAS_RX_BIST_START 0x00000001 /* Start BIST process. */
444 #define CAS_RX_BIST_SM 0x00007800 /* BIST state machine */
489 #define CAS_HP_RAM_BIST 0x419c /* HP RAM BIST */
541 #define CAS_HP_RAM_BIST_START 0x00000001 /* Start RAM BIST process. */
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/
H A Dfsl,imx23-digctl.yaml16 - BIST controls for ARM Core and On-Chip RAM
/freebsd/sys/dev/mvs/
H A Dmvs.h318 #define SATA_BISTC 0x334 /* BIST Control */
319 #define SATA_BISTDW1 0x338 /* BIST DW1 */
320 #define SATA_BISTDW2 0x33c /* BIST DW2 */
368 #define SATA_FISC_FISWAIT4HOSTRDYEN_B3 (1 << 11) /* BIST Acivate FIS */
/freebsd/sys/dev/pms/RefTisa/sallsdk/api/
H A Dsa_spec.h157 /** \brief Structure for SATA BIST FIS
160 * for FIS type BIST (Built In Self Test) Activate Bidirectional.
181 bit8 fisType; /* fisType, set to 58h for BIST */
259 agsaFisBISTHeader_t Bist; member
269 bit8 data[8]; /* BIST data */
398 agsaFisBIST_t fisBIST; /* Structure containing the FIS request for BIST */
/freebsd/share/man/man9/
H A Dbhnd.9970 Initiate a built-in self-test (BIST).
971 Must be cleared after BIST results are read via the IOST (I/O Status) register.
996 Set upon BIST completion.
1002 Set upon detection of a BIST error; the value is unspecified if BIST has not
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_mcp_api.h1183 * @brief Bist register test
1194 * @brief Bist clock test
1205 * @brief Bist nvm test - get number of images
1219 * @brief Bist nvm test - get image attributes by index
H A Dreg_addr.h272 … (0xff<<24) // The BIST register functions are not supported. All 8 bits …
274 … 0x00000cUL //Access:RW DataWidth:0x20 // BIST, Header Type, Cache…
283 …E_LINE_SIZE_REG_BIST_K2 (0xff<<24) // Optional for BIST support.
292 …BIST register is used to initiate and report the results of any Built-In-Self-Test. This value can…
4703 … (0xff<<16) // This register controls the read value of the bist register in the con…
9383 … (0xff<<24) // The BIST register functions are not supported. All 8 bits …
9385 … 0x00000cUL //Access:R DataWidth:0x20 // BIST, Header Type, Cache…
9394 …Y_CACHE_LINE_SIZE_REG_BIST_K2 (0xff<<24) // Optional for BIST support.
10426 …BIST mode. When set, BIST testing will be performed and the results will be posted upon completion…
10427 … // Provides a threshold for the number of CAM BIST errors that are acceptable before reporting C…
[all …]
/freebsd/sys/dev/bfe/
H A Dif_bfereg.h268 #define BFE_BE 0x80000000 /* BIST Enable */
275 #define BFE_BISTF 0x40000000 /* BIST Failed */
276 #define BFE_BISTD 0x80000000 /* BIST Done */
/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsaport.c1280 agsaEncryptBist_t bist; in saEncryptSelftestExecute() local
1282 si_memset(&bist, 0, (sizeof(agsaEncryptBist_t))); in saEncryptSelftestExecute()
1285 bist.r_subop = (type & 0xFF); in saEncryptSelftestExecute()
1287 si_memcpy(&bist.testDiscption,TestDescriptor,length ); in saEncryptSelftestExecute()
1290 ret = mpiEncryptBistCmd( agRoot, queueNum, agContext, &bist ); in saEncryptSelftestExecute()
H A Dsampicmd.c2548 agsaEncryptBist_t *bist ) in mpiEncryptBistCmd() argument
2581 bist->tag = pRequest->HTag; in mpiEncryptBistCmd()
2585 bist->tag, in mpiEncryptBistCmd()
2586 bist->r_subop, in mpiEncryptBistCmd()
2587 bist->testDiscption[0], in mpiEncryptBistCmd()
2588 bist->testDiscption[1], in mpiEncryptBistCmd()
2589 bist->testDiscption[2], in mpiEncryptBistCmd()
2590 bist->testDiscption[3], in mpiEncryptBistCmd()
2591 bist->testDiscption[4] )); in mpiEncryptBistCmd()
2592 …ret = mpiBuildCmd(agRoot, (bit32 *)bist , MPI_CATEGORY_SAS_SATA, OPC_INB_ENC_TEST_EXECUTE, IOMB_SI… in mpiEncryptBistCmd()
H A Dsaproto.h831 agsaEncryptBist_t *bist );
/freebsd/sys/dev/ale/
H A Dif_alereg.h160 /* Packet memory BIST. */
166 /* PCIe retry buffer BIST. */
/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h142 #define BHND_PCIE_BIST_STATUS 0x00C /**< BIST status */
277 #define BHND_PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
/freebsd/sys/dev/isci/scil/
H A Dintel_sata.h230 * @brief SATA BIST Activate FIS
/freebsd/sys/dev/bhnd/
H A Dbhnd.h110 BHND_IOCTL_BIST = 0x8000, /**< Initiate a built-in self-test (BIST). Must be cleared
111 after BIST results are read via BHND_IOST_BIST_* */
127 BHND_IOST_BIST_DONE = 0x8000, /**< Set upon BIST completion (see BHND_IOCTL_BIST), and cleared
129 BHND_IOST_BIST_FAIL = 0x4000, /**< Set upon detection of a BIST error; the value is unspecified
130 if BIST has not completed and BHND_IOST_BIST_DONE is not set. */
/freebsd/sys/dev/alc/
H A Dif_alcreg.h285 /* Packet memory BIST. */
291 /* PCIe retry buffer BIST. */
/freebsd/sys/dev/arcmsr/
H A Darcmsr.h2847 ** ATU BIST Register - ATUBISTR
2849 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is
2850 ** initiated. This register is the interface between the host processor requesting BIST functions …
2851 ** the 80331 replying with the results from the software implementation of the BIST functionality.
2854 …* 07 0 2 BIST Capable - This bit value is always equal to the AT…
2855 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit i…
2856 …tting this bit generates an interrupt to the Intel XScale core to perform a software BIST function.
2857 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST r…
2859 ** When the ATUCR BIST Interrupt Enable bit is clear:
2860 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST funct…
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h397 #define BWN_NPHY_BIST_STAT2 BWN_PHY_N(0x0EA) /* BIST status 2 */
398 #define BWN_NPHY_BIST_STAT3 BWN_PHY_N(0x0EB) /* BIST status 3 */
523 #define BWN_NPHY_BIST_STAT4 BWN_PHY_N(0x156) /* BIST status 4 */

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