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/linux/lib/
H A Dbch.c2 * Generic binary BCH encoding/decoding library
24 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
33 * On systems supporting hw BCH features, intermediate results may be provided
40 * (m,t) are fixed and known in advance, e.g. when using BCH error correction
76 #include <linux/bch.h>
118 static u8 swap_bits(struct bch_control *bch, u8 in) in swap_bits() argument
120 if (!bch->swap_bits) in swap_bits()
129 static void bch_encode_unaligned(struct bch_control *bch, in bch_encode_unaligned() argument
135 const int l = BCH_ECC_WORDS(bch)-1; in bch_encode_unaligned()
138 u8 tmp = swap_bits(bch, *data++); in bch_encode_unaligned()
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/linux/drivers/mtd/nand/raw/ingenic/
H A Djz4725b_bch.c3 * JZ4725B BCH controller driver
59 /* Timeout for BCH calculation/correction. */
62 static inline void jz4725b_bch_config_set(struct ingenic_ecc *bch, u32 cfg) in jz4725b_bch_config_set() argument
64 writel(cfg, bch->base + BCH_BHCSR); in jz4725b_bch_config_set()
67 static inline void jz4725b_bch_config_clear(struct ingenic_ecc *bch, u32 cfg) in jz4725b_bch_config_clear() argument
69 writel(cfg, bch->base + BCH_BHCCR); in jz4725b_bch_config_clear()
72 static int jz4725b_bch_reset(struct ingenic_ecc *bch, in jz4725b_bch_reset() argument
78 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4725b_bch_reset()
80 /* Initialise and enable BCH. */ in jz4725b_bch_reset()
81 jz4725b_bch_config_clear(bch, 0x1f); in jz4725b_bch_reset()
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H A Djz4780_bch.c3 * JZ4780 BCH controller driver
59 /* Timeout for BCH calculation/correction. */
62 static void jz4780_bch_reset(struct ingenic_ecc *bch, in jz4780_bch_reset() argument
68 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4780_bch_reset()
70 /* Set up BCH count register. */ in jz4780_bch_reset()
73 writel(reg, bch->base + BCH_BHCNT); in jz4780_bch_reset()
75 /* Initialise and enable BCH. */ in jz4780_bch_reset()
80 writel(reg, bch->base + BCH_BHCR); in jz4780_bch_reset()
83 static void jz4780_bch_disable(struct ingenic_ecc *bch) in jz4780_bch_disable() argument
85 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4780_bch_disable()
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H A DKconfig8 based boards, using the BCH controller for hardware error correction.
16 tristate "Hardware BCH support for JZ4740 SoC"
26 tristate "Hardware BCH support for JZ4725B SoC"
29 Enable this driver to support the BCH error-correction hardware
33 will be called jz4725b-bch.
36 tristate "Hardware BCH support for JZ4780 SoC"
39 Enable this driver to support the BCH error-correction hardware
43 will be called jz4780-bch.
/linux/drivers/isdn/mISDN/
H A Dhwchannel.c39 struct bchannel *bch = container_of(ws, struct bchannel, workq); in bchannel_bh() local
43 if (test_and_clear_bit(FLG_RECVQUEUE, &bch->Flags)) { in bchannel_bh()
44 while ((skb = skb_dequeue(&bch->rqueue))) { in bchannel_bh()
45 bch->rcount--; in bchannel_bh()
46 if (likely(bch->ch.peer)) { in bchannel_bh()
47 err = bch->ch.recv(bch->ch.peer, skb); in bchannel_bh()
156 mISDN_ctrl_bchannel(struct bchannel *bch, struct mISDN_ctrl_req *cq) in mISDN_ctrl_bchannel() argument
167 memset(bch->fill, cq->p2 & 0xff, MISDN_BCH_FILL_SIZE); in mISDN_ctrl_bchannel()
168 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags); in mISDN_ctrl_bchannel()
170 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); in mISDN_ctrl_bchannel()
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H A Dl1oip_core.c355 struct bchannel *bch; in l1oip_socket_recv() local
377 bch = hc->chan[channel].bch; in l1oip_socket_recv()
378 if (!dch && !bch) { in l1oip_socket_recv()
406 if (bch) { in l1oip_socket_recv()
436 queue_ch_frame(&bch->ch, PH_DATA_IND, rx_counter, nskb); in l1oip_socket_recv()
1008 struct bchannel *bch; in open_bchannel() local
1016 bch = hc->chan[ch].bch; in open_bchannel()
1017 if (!bch) { in open_bchannel()
1018 printk(KERN_ERR "%s:internal error ch %d has no bch\n", in open_bchannel()
1022 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) in open_bchannel()
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/linux/drivers/isdn/hardware/mISDN/
H A Davmfritz.c130 struct bchannel bch[2]; member
141 card->bch[0].debug = debug; in _set_debug()
142 card->bch[1].debug = debug; in _set_debug()
251 if (test_bit(FLG_ACTIVE, &fc->bch[0].Flags) && in Sel_BCS()
252 (fc->bch[0].nr & channel)) in Sel_BCS()
253 return &fc->bch[0]; in Sel_BCS()
254 else if (test_bit(FLG_ACTIVE, &fc->bch[1].Flags) && in Sel_BCS()
255 (fc->bch[1].nr & channel)) in Sel_BCS()
256 return &fc->bch[1]; in Sel_BCS()
276 write_ctrl(struct bchannel *bch, int which) { in write_ctrl() argument
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H A DmISDNisar.c69 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) { in send_mbox()
98 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) { in rcv_mbox()
175 u32 saved_debug = isar->ch[0].bch.debug; in load_firmware()
194 isar->ch[0].bch.debug &= ~DEBUG_HW_BFIFO; in load_firmware()
281 isar->ch[0].bch.debug = saved_debug; in load_firmware()
393 isar->ch[0].bch.debug = saved_debug; in load_firmware()
405 _queue_data(&ch->bch.ch, PH_CONTROL_IND, status, 0, NULL, GFP_ATOMIC); in deliver_status()
419 if (test_bit(FLG_RX_OFF, &ch->bch.Flags)) { in isar_rcv_frame()
420 ch->bch.dropcnt += ch->is->clsb; in isar_rcv_frame()
424 switch (ch->bch.state) { in isar_rcv_frame()
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H A Dnetjet.c42 struct bchannel bch; member
96 card->bc[0].bch.debug = debug; in _set_debug()
97 card->bc[1].bch.debug = debug; in _set_debug()
178 struct tiger_hw *card = bc->bch.hw; in fill_mem()
182 bc->bch.nr, fill, cnt, idx, card->send.idx); in fill_mem()
183 if (bc->bch.nr & 2) { in fill_mem()
201 struct tiger_hw *card = bc->bch.hw; in mode_tiger()
204 bc->bch.nr, bc->bch.state, protocol); in mode_tiger()
207 if (bc->bch.state == ISDN_P_NONE) in mode_tiger()
210 bc->bch.state = protocol; in mode_tiger()
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H A Dw6692.c45 struct bchannel bch; member
83 card->bc[0].bch.debug = debug; in _set_debug()
84 card->bc[1].bch.debug = debug; in _set_debug()
448 struct w6692_hw *card = wch->bch.hw; in W6692_empty_Bfifo()
453 if (unlikely(wch->bch.state == ISDN_P_NONE)) { in W6692_empty_Bfifo()
456 if (wch->bch.rx_skb) in W6692_empty_Bfifo()
457 skb_trim(wch->bch.rx_skb, 0); in W6692_empty_Bfifo()
460 if (test_bit(FLG_RX_OFF, &wch->bch.Flags)) { in W6692_empty_Bfifo()
461 wch->bch.dropcnt += count; in W6692_empty_Bfifo()
465 maxlen = bchannel_get_rxbuf(&wch->bch, count); in W6692_empty_Bfifo()
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H A Dhfcpci.c135 struct bchannel bch[2]; member
310 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) && in Sel_BCS()
311 (hc->bch[0].nr & channel)) in Sel_BCS()
312 return &hc->bch[0]; in Sel_BCS()
313 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) && in Sel_BCS()
314 (hc->bch[1].nr & channel)) in Sel_BCS()
315 return &hc->bch[1]; in Sel_BCS()
368 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL) in hfcpci_clear_fifo_tx()
382 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL) in hfcpci_clear_fifo_tx()
394 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz, in hfcpci_empty_bfifo() argument
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H A DmISDNipac.c886 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr, in waitforCEC()
889 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr); in waitforCEC()
906 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr, in waitforXFW()
909 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr); in waitforXFW()
929 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count); in hscx_empty_fifo()
930 if (test_bit(FLG_RX_OFF, &hscx->bch.Flags)) { in hscx_empty_fifo()
931 hscx->bch.dropcnt += count; in hscx_empty_fifo()
935 maxlen = bchannel_get_rxbuf(&hscx->bch, count); in hscx_empty_fifo()
938 if (hscx->bch.rx_skb) in hscx_empty_fifo()
939 skb_trim(hscx->bch.rx_skb, 0); in hscx_empty_fifo()
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H A Dhfcsusb.c48 static int hfcsusb_setup_bch(struct bchannel *bch, int protocol);
49 static void deactivate_bchannel(struct bchannel *bch);
199 struct bchannel *bch = container_of(ch, struct bchannel, ch); in hfcusb_l2l1B() local
200 struct hfcsusb *hw = bch->hw; in hfcusb_l2l1B()
211 ret = bchannel_senddata(bch, skb); in hfcusb_l2l1B()
220 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { in hfcusb_l2l1B()
221 hfcsusb_start_endpoint(hw, bch->nr - 1); in hfcusb_l2l1B()
222 ret = hfcsusb_setup_bch(bch, ch->protocol); in hfcusb_l2l1B()
230 deactivate_bchannel(bch); in hfcusb_l2l1B()
252 phi = kzalloc(struct_size(phi, bch, dch->dev.nrbchan), GFP_ATOMIC); in hfcsusb_ph_info()
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/linux/Documentation/devicetree/bindings/mtd/
H A Dgpmi-nand.yaml37 - description: Address and length of bch block.
42 - const: bch
48 const: bch
128 - description: SoC gpmi bch clock
129 - description: SoC gpmi bch apb clock
130 - description: SoC per1 bch clock
149 - description: SoC gpmi bch apb clock
167 - description: SoC gpmi bch clock
168 - description: SoC gpmi bch apb clock
183 reg-names = "gpmi-nand", "bch";
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H A Dnvidia-tegra20-nand.txt28 Supported values with "hw" ECC mode are: "rs", "bch".
35 - BCH: 4, 8, 14, 16
60 nand-ecc-algo = "bch";
/linux/drivers/mtd/nand/
H A Decc-sw-bch.c4 * using binary BCH codes. It relies on the generic BCH library lib/bch.c.
15 #include <linux/mtd/nand-ecc-sw-bch.h>
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
57 count = bch_decode(engine_conf->bch, NULL, step_size, read_ecc, in nand_ecc_sw_bch_correct()
79 * nand_ecc_sw_bch_cleanup - Cleanup software BCH ECC resources
86 bch_free(engine_conf->bch); in nand_ecc_sw_bch_cleanup()
92 * nand_ecc_sw_bch_init - Initialize software BCH ECC engine
95 * Returns: a pointer to a new NAND BCH control structure, or NULL upon failure
97 * Initialize NAND BCH error correction. @nand.ecc parameters 'step_size' and
98 * 'bytes' are used to compute the following BCH parameters:
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H A DKconfig27 more strength correction and in this case BCH or RS will be
39 bool "Software BCH ECC engine"
40 select BCH
44 This enables support for software BCH error correction. Binary BCH
/linux/drivers/md/bcache/
H A Dfeatures.h40 BCH##_FEATURE_COMPAT_##flagname) != 0); \
45 BCH##_FEATURE_COMPAT_##flagname; \
50 ~BCH##_FEATURE_COMPAT_##flagname; \
59 BCH##_FEATURE_RO_COMPAT_##flagname) != 0); \
64 BCH##_FEATURE_RO_COMPAT_##flagname; \
69 ~BCH##_FEATURE_RO_COMPAT_##flagname; \
78 BCH##_FEATURE_INCOMPAT_##flagname) != 0); \
83 BCH##_FEATURE_INCOMPAT_##flagname; \
88 ~BCH##_FEATURE_INCOMPAT_##flagname; \
/linux/include/linux/mtd/
H A Dnand-ecc-sw-bch.h5 * This file is the header for the NAND BCH ECC implementation.
12 #include <linux/bch.h>
15 * struct nand_ecc_sw_bch_conf - private software BCH ECC engine structure
21 * @bch: BCH control structure
30 struct bch_control *bch; member
/linux/include/linux/
H A Dbch.h3 * Generic binary BCH encoding/decoding library
12 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
20 * struct bch_control - BCH control structure
61 void bch_free(struct bch_control *bch);
63 void bch_encode(struct bch_control *bch, const uint8_t *data,
66 int bch_decode(struct bch_control *bch, const uint8_t *data, unsigned int len,
/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.c22 #include "bch-regs.h"
26 #define GPMI_NAND_BCH_REGS_ADDR_RES_NAME "bch"
27 #define GPMI_NAND_BCH_INTERRUPT_RES_NAME "bch"
67 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
68 * If you try to soft reset the BCH block, it becomes unusable until
70 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
71 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
161 * Reset BCH here, too. We got failures otherwise :( in gpmi_init()
162 * See later BCH reset for explanation of MX23 and MX28 handling in gpmi_init()
178 /* Select BCH ECC. */ in gpmi_init()
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H A Dgpmi-nand.h26 * struct bch_geometry - BCH geometry description.
134 /* BCH */
149 bool bch; member
166 /* BCH : Status Block Completion Codes */
/linux/drivers/mtd/devices/
H A Ddocg3.c21 #include <linux/bch.h>
41 * - a 7 bytes BCH code stored in the OOB for each page
42 * The BCH ECC is :
43 * - BCH is in GF(2^14)
44 * - BCH is over data of 520 bytes (512 page + 7 page_info bytes
46 * - BCH can correct up to 4 bits (t = 4)
47 * - BCH syndroms are calculated in hardware, and checked in hardware as well
62 /* byte 7 is Hamming ECC, byte 8-14 are BCH ECC */ in docg3_ooblayout_ecc()
550 * @len: the number of bytes covered by the ECC (BCH covered)
553 * ECC (on 1 byte) and the BCH hardware ECC (on 7 bytes).
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/linux/drivers/mtd/nand/raw/
H A Darasan-nand-controller.c13 #include <linux/bch.h>
164 * @errloc: Array of errors located with soft BCH
166 * @bch: BCH structure
187 struct bch_control *bch; member
388 * The hardware BCH ECC engine is known to be inconstent in BCH mode and never
390 * software BCH implementation in the read path.
448 * For each step, compute by softare the BCH syndrome over the raw data. in anfc_read_page_hw_ecc()
463 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size, in anfc_read_page_hw_ecc()
1186 anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true); in anfc_init_hw_ecc_controller()
1187 if (!anand->bch) in anfc_init_hw_ecc_controller()
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H A DKconfig52 bool "Support hardware based BCH error correction"
54 select BCH
57 locate and correct errors when using BCH ECC scheme. This offloads
219 The GPMI controller is very powerful, with the help of BCH
411 select BCH

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