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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dnv50.c69 nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4); in nv50_bar_bar1_init()
168 /* BAR1 */ in nv50_bar_oneinit()
176 &bar1_lock, "bar1", &bar->bar1_vmm); in nv50_bar_oneinit()
187 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1); in nv50_bar_oneinit()
191 nvkm_kmap(bar->bar1); in nv50_bar_oneinit()
192 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000); in nv50_bar_oneinit()
193 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
194 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
195 nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
197 nvkm_wo32(bar->bar1, 0x10, 0x00000000); in nv50_bar_oneinit()
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H A Dbase.c36 return device->bar->func->bar1.vmm(device->bar); in nvkm_bar_bar1_vmm()
44 bar->func->bar1.init(bar); in nvkm_bar_bar1_reset()
45 bar->func->bar1.wait(bar); in nvkm_bar_bar1_reset()
100 if (bar->func->bar1.fini) in nvkm_bar_fini()
101 bar->func->bar1.fini(bar); in nvkm_bar_fini()
113 bar->func->bar1.init(bar); in nvkm_bar_init()
114 bar->func->bar1.wait(bar); in nvkm_bar_init()
H A Dgf100.c103 (bar_id == NVKM_BAR2_INST) ? "bar2" : "bar1", &bar_vm->vmm); in gf100_bar_oneinit_bar()
140 /* BAR1 */ in gf100_bar_oneinit()
180 .bar1.init = gf100_bar_bar1_init,
181 .bar1.fini = gf100_bar_bar1_fini,
182 .bar1.wait = gf100_bar_bar1_wait,
183 .bar1.vmm = gf100_bar_bar1_vmm,
H A Dgm107.c50 .bar1.init = gf100_bar_bar1_init,
51 .bar1.fini = gf100_bar_bar1_fini,
52 .bar1.wait = gm107_bar_bar1_wait,
53 .bar1.vmm = gf100_bar_bar1_vmm,
H A Dg84.c47 .bar1.init = nv50_bar_bar1_init,
48 .bar1.fini = nv50_bar_bar1_fini,
49 .bar1.wait = nv50_bar_bar1_wait,
50 .bar1.vmm = nv50_bar_bar1_vmm,
H A Dtu102.c84 .bar1.init = tu102_bar_bar1_init,
85 .bar1.fini = tu102_bar_bar1_fini,
86 .bar1.wait = tu102_bar_bar1_wait,
87 .bar1.vmm = gf100_bar_bar1_vmm,
H A Dgm20b.c28 .bar1.init = gf100_bar_bar1_init,
29 .bar1.wait = gm107_bar_bar1_wait,
30 .bar1.vmm = gf100_bar_bar1_vmm,
H A Dgk20a.c28 .bar1.init = gf100_bar_bar1_init,
29 .bar1.wait = gf100_bar_bar1_wait,
30 .bar1.vmm = gf100_bar_bar1_vmm,
/linux/drivers/media/pci/cobalt/
H A Dcobalt-driver.h125 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE)
127 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x100)
129 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x200)
131 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x300)
133 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x400)
135 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x500)
137 #define COBALT_TX_BASE(cobalt) (cobalt->bar1 + COBALT_VID_BASE + 0x5000)
257 void __iomem *bar0, *bar1; member
309 iowrite32(val, cobalt->bar1 + reg); in cobalt_write_bar1()
314 return ioread32(cobalt->bar1 + reg); in cobalt_read_bar1()
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H A Dcobalt-i2c.c88 (cobalt->bar1 + COBALT_I2C_0_BASE); in cobalt_i2c_regs()
91 (cobalt->bar1 + COBALT_I2C_1_BASE); in cobalt_i2c_regs()
94 (cobalt->bar1 + COBALT_I2C_2_BASE); in cobalt_i2c_regs()
97 (cobalt->bar1 + COBALT_I2C_3_BASE); in cobalt_i2c_regs()
100 (cobalt->bar1 + COBALT_I2C_HSMA_BASE); in cobalt_i2c_regs()
H A Dcobalt-driver.c285 if (cobalt->bar1) { in cobalt_pci_iounmap()
286 pci_iounmap(pci_dev, cobalt->bar1); in cobalt_pci_iounmap()
287 cobalt->bar1 = NULL; in cobalt_pci_iounmap()
353 cobalt->bar1 = pci_iomap(pci_dev, 1, 0); in cobalt_setup_pci()
354 if (cobalt->bar1 == NULL) { in cobalt_setup_pci()
355 cobalt->bar1 = pci_iomap(pci_dev, 2, 0); in cobalt_setup_pci()
358 if (!cobalt->bar0 || !cobalt->bar1) { in cobalt_setup_pci()
407 ioread8(cobalt->bar1 + COBALT_HDL_INFO_BASE + i); in cobalt_hdl_info_get()
/linux/arch/mips/include/asm/octeon/
H A Dpci-octeon.h15 * The physical memory base mapped by BAR1. 256MB at the end of the
22 * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
23 * place BAR1 so it is the same for both.
41 * For PCI (not PCIe) the base of the memory mapped by BAR1
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_mem_ops.h27 /** Read a 64-bit value from a BAR1 mapped core memory address.
31 * The range_idx gives the BAR1 index register for the range of address
38 /** Read a 32-bit value from a BAR1 mapped core memory address.
46 /** Write a 32-bit value to a BAR1 mapped core memory address.
H A Dcn23xx_pf_device.c874 u64 bar1; in cn23xx_bar1_idx_setup() local
880 WRITE_ONCE(bar1, reg_adr); in cn23xx_bar1_idx_setup()
881 lio_pci_writeq(oct, (READ_ONCE(bar1) & 0xFFFFFFFEULL), in cn23xx_bar1_idx_setup()
885 WRITE_ONCE(bar1, reg_adr); in cn23xx_bar1_idx_setup()
895 WRITE_ONCE(bar1, lio_pci_readq( in cn23xx_bar1_idx_setup()
1141 u64 BAR0, BAR1; in setup_cn23xx_octeon_pf_device() local
1148 BAR1 = (u64)(data32 & ~0xf); in setup_cn23xx_octeon_pf_device()
1150 BAR1 |= ((u64)data32 << 32); in setup_cn23xx_octeon_pf_device()
1152 if (!BAR0 || !BAR1) { in setup_cn23xx_octeon_pf_device()
1155 if (!BAR1) in setup_cn23xx_octeon_pf_device()
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dbase.c305 /* Allocate USERD + BAR1 polling area. */ in nvkm_fifo_oneinit()
307 struct nvkm_vmm *bar1 = nvkm_bar_bar1_vmm(device); in nvkm_fifo_oneinit() local
315 ret = nvkm_vmm_get(bar1, 12, nvkm_memory_size(fifo->userd.mem), &fifo->userd.bar1); in nvkm_fifo_oneinit()
319 ret = nvkm_memory_map(fifo->userd.mem, 0, bar1, fifo->userd.bar1, NULL, 0); in nvkm_fifo_oneinit()
340 if (fifo->userd.bar1) in nvkm_fifo_dtor()
341 nvkm_vmm_put(nvkm_bar_bar1_vmm(engine->subdev.device), &fifo->userd.bar1); in nvkm_fifo_dtor()
/linux/tools/testing/selftests/net/
H A Dunicast_extensions.sh77 # [foo] <---> [foo1]-[bar1] <---> [bar] /prefix
84 # containing linked veth devices foo-foo1, bar1-bar
85 # (foo in $foo_ns, foo1 and bar1 in $router_ns, and
96 ip -n $router_ns address add $3/$5 dev bar1 || return 1
97 ip -n $router_ns link set bar1 up || return 1
135 # [foo] <---> [foo1]-[bar1] <---> [bar] /prefix
142 ip link add bar netns $bar_ns type veth peer name bar1 netns $router_ns
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Dbar.c177 rm->bar1.init = r535_bar_bar1_init; in r535_bar_new_()
178 rm->bar1.fini = r535_bar_bar1_fini; in r535_bar_new_()
179 rm->bar1.wait = r535_bar_bar1_wait; in r535_bar_new_()
180 rm->bar1.vmm = hw->bar1.vmm; in r535_bar_new_()
/linux/drivers/misc/bcm-vk/
H A Dbcm_vk.h198 * BAR1
201 /* BAR1 message q definition */
203 /* indicate if msgq ctrl in BAR1 is populated */
209 /* number of msgqs in BAR1 */
211 /* BAR1 queue control structure offset */
214 /* BAR1 ucode and boot1 version tag */
230 /* BAR1 DAUTH info */
241 /* BAR1 SOTP AUTH and REVID info */
/linux/drivers/misc/rp1/
H A Drp1_pci.c41 void __iomem *bar1; member
47 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq)); in msix_cfg_set()
52 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); in msix_cfg_clr()
218 rp1->bar1 = pcim_iomap(pdev, 1, 0); in rp1_probe()
219 if (!rp1->bar1) { in rp1_probe()
/linux/Documentation/translations/it_IT/doc-guide/
H A Dparse-headers.rst165 enum foo { BAR1, BAR2, PRIVATE };
169 replace symbol BAR1 :c:type:\`foo\`
175 enum foo { BAR1, BAR2, PRIVATE };
177 Genererà un riferimento ai valori BAR1 e BAR2 dal simbolo foo nel dominio C.
/linux/Documentation/translations/zh_CN/doc-guide/
H A Dparse-headers.rst153 enum foo { BAR1, BAR2, PRIVATE };
157 replace symbol BAR1 :c:type:\`foo\`
163 enum foo { BAR1, BAR2, PRIVATE };
/linux/sound/pci/lola/
H A Dlola_proc.c171 snd_iprintf(buffer, "BAR1 %02x: %08x\n", i, in lola_proc_regs_read()
172 readl(chip->bar[BAR1].remap_addr + i)); in lola_proc_regs_read()
176 snd_iprintf(buffer, "BAR1 %02x: %08x\n", i, in lola_proc_regs_read()
177 readl(chip->bar[BAR1].remap_addr + i)); in lola_proc_regs_read()
/linux/arch/mips/pci/
H A Dpci-octeon.c395 /* BAR1 hole */ in octeon_pci_initialize()
397 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ in octeon_pci_initialize()
400 ctl_status_2.s.bb1 = 1; /* BAR1 is big */ in octeon_pci_initialize()
546 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are in octeon_pci_initialize()
612 * with BAR0/BAR1 during these reads. in octeon_pci_setup()
631 /* BAR1 movable mappings set for identity mapping */ in octeon_pci_setup()
650 /* Devices go after BAR1 */ in octeon_pci_setup()
665 /* BAR1 movable regions contiguous to cover the swiotlb */ in octeon_pci_setup()
/linux/arch/mips/cavium-octeon/
H A Ddma-octeon.c93 /* Anything in the BAR1 hole or above goes via BAR2 */ in octeon_big_phys_to_dma()
121 /* Anything not in the BAR1 range goes via BAR2 */ in octeon_small_phys_to_dma()
226 * memory past the BAR1 hole. in plat_swiotlb_setup()
/linux/drivers/scsi/aacraid/
H A Dsrc.c621 iounmap(dev->regs.src.bar1); in aac_src_ioremap()
622 dev->regs.src.bar1 = NULL; in aac_src_ioremap()
627 dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2), in aac_src_ioremap()
630 if (dev->regs.src.bar1 == NULL) in aac_src_ioremap()
634 iounmap(dev->regs.src.bar1); in aac_src_ioremap()
635 dev->regs.src.bar1 = NULL; in aac_src_ioremap()
657 dev->regs.src.bar1 = in aac_srcv_ioremap()
660 if (dev->regs.src.bar1 == NULL) in aac_srcv_ioremap()
664 iounmap(dev->regs.src.bar1); in aac_srcv_ioremap()
665 dev->regs.src.bar1 = NULL; in aac_srcv_ioremap()
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