| /linux/drivers/media/pci/cobalt/ |
| H A D | cobalt-driver.h | 125 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE)
127 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x100)
129 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x200)
131 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x300)
133 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x400)
135 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x500)
137 #define COBALT_TX_BASE(cobalt) (cobalt->bar1 + COBALT_VID_BASE + 0x5000)
257 void __iomem *bar0, *bar1; member
309 iowrite32(val, cobalt->bar1 + reg); in cobalt_write_bar1()
314 return ioread32(cobalt->bar1 + reg); in cobalt_read_bar1()
[all …]
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| H A D | cobalt-i2c.c | 88 (cobalt->bar1 + COBALT_I2C_0_BASE); in cobalt_i2c_regs()
91 (cobalt->bar1 + COBALT_I2C_1_BASE); in cobalt_i2c_regs()
94 (cobalt->bar1 + COBALT_I2C_2_BASE); in cobalt_i2c_regs()
97 (cobalt->bar1 + COBALT_I2C_3_BASE); in cobalt_i2c_regs()
100 (cobalt->bar1 + COBALT_I2C_HSMA_BASE); in cobalt_i2c_regs()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bar/ |
| H A D | base.c | 36 return device->bar->func->bar1.vmm(device->bar); in nvkm_bar_bar1_vmm()
44 bar->func->bar1.init(bar); in nvkm_bar_bar1_reset()
45 bar->func->bar1.wait(bar); in nvkm_bar_bar1_reset()
100 if (bar->func->bar1.fini) in nvkm_bar_fini()
101 bar->func->bar1.fini(bar); in nvkm_bar_fini()
113 bar->func->bar1.init(bar); in nvkm_bar_init()
114 bar->func->bar1.wait(bar); in nvkm_bar_init()
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| H A D | gm107.c | 50 .bar1.init = gf100_bar_bar1_init,
51 .bar1.fini = gf100_bar_bar1_fini,
52 .bar1.wait = gm107_bar_bar1_wait,
53 .bar1.vmm = gf100_bar_bar1_vmm,
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| H A D | g84.c | 47 .bar1.init = nv50_bar_bar1_init,
48 .bar1.fini = nv50_bar_bar1_fini,
49 .bar1.wait = nv50_bar_bar1_wait,
50 .bar1.vmm = nv50_bar_bar1_vmm,
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| H A D | tu102.c | 84 .bar1.init = tu102_bar_bar1_init,
85 .bar1.fini = tu102_bar_bar1_fini,
86 .bar1.wait = tu102_bar_bar1_wait,
87 .bar1.vmm = gf100_bar_bar1_vmm,
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| H A D | gm20b.c | 28 .bar1.init = gf100_bar_bar1_init,
29 .bar1.wait = gm107_bar_bar1_wait,
30 .bar1.vmm = gf100_bar_bar1_vmm,
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| H A D | gk20a.c | 28 .bar1.init = gf100_bar_bar1_init,
29 .bar1.wait = gf100_bar_bar1_wait,
30 .bar1.vmm = gf100_bar_bar1_vmm,
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| /linux/arch/mips/include/asm/octeon/ |
| H A D | pci-octeon.h | 15 * The physical memory base mapped by BAR1. 256MB at the end of the
22 * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
23 * place BAR1 so it is the same for both.
41 * For PCI (not PCIe) the base of the memory mapped by BAR1
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| /linux/drivers/net/ethernet/cavium/liquidio/ |
| H A D | octeon_mem_ops.h | 27 /** Read a 64-bit value from a BAR1 mapped core memory address.
31 * The range_idx gives the BAR1 index register for the range of address
38 /** Read a 32-bit value from a BAR1 mapped core memory address.
46 /** Write a 32-bit value to a BAR1 mapped core memory address.
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| H A D | cn23xx_pf_device.c | 874 u64 bar1; in cn23xx_bar1_idx_setup() local
880 WRITE_ONCE(bar1, reg_adr); in cn23xx_bar1_idx_setup()
881 lio_pci_writeq(oct, (READ_ONCE(bar1) & 0xFFFFFFFEULL), in cn23xx_bar1_idx_setup()
885 WRITE_ONCE(bar1, reg_adr); in cn23xx_bar1_idx_setup()
895 WRITE_ONCE(bar1, lio_pci_readq( in cn23xx_bar1_idx_setup()
1141 u64 BAR0, BAR1; in setup_cn23xx_octeon_pf_device() local
1148 BAR1 = (u64)(data32 & ~0xf); in setup_cn23xx_octeon_pf_device()
1150 BAR1 |= ((u64)data32 << 32); in setup_cn23xx_octeon_pf_device()
1152 if (!BAR0 || !BAR1) { in setup_cn23xx_octeon_pf_device()
1155 if (!BAR1) in setup_cn23xx_octeon_pf_device()
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| H A D | base.c | 305 /* Allocate USERD + BAR1 polling area. */ in nvkm_fifo_oneinit()
307 struct nvkm_vmm *bar1 = nvkm_bar_bar1_vmm(device); in nvkm_fifo_oneinit() local
315 ret = nvkm_vmm_get(bar1, 12, nvkm_memory_size(fifo->userd.mem), &fifo->userd.bar1); in nvkm_fifo_oneinit()
319 ret = nvkm_memory_map(fifo->userd.mem, 0, bar1, fifo->userd.bar1, NULL, 0); in nvkm_fifo_oneinit()
340 if (fifo->userd.bar1) in nvkm_fifo_dtor()
341 nvkm_vmm_put(nvkm_bar_bar1_vmm(engine->subdev.device), &fifo->userd.bar1); in nvkm_fifo_dtor()
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| /linux/tools/testing/selftests/net/ |
| H A D | unicast_extensions.sh | 77 # [foo] <---> [foo1]-[bar1] <---> [bar] /prefix
84 # containing linked veth devices foo-foo1, bar1-bar
85 # (foo in $foo_ns, foo1 and bar1 in $router_ns, and
96 ip -n $router_ns address add $3/$5 dev bar1 || return 1
97 ip -n $router_ns link set bar1 up || return 1
135 # [foo] <---> [foo1]-[bar1] <---> [bar] /prefix
142 ip link add bar netns $bar_ns type veth peer name bar1 netns $router_ns
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| /linux/sound/pci/lola/ |
| H A D | lola.c | 226 status = lola_readl(chip, BAR1, DINTSTS); in lola_interrupt()
230 in_sts = lola_readl(chip, BAR1, DIINTSTS); in lola_interrupt()
231 out_sts = lola_readl(chip, BAR1, DOINTSTS); in lola_interrupt()
276 lola_writel(chip, BAR1, DINTSTS, in lola_interrupt()
300 lola_writel(chip, BAR1, BOARD_MODE, 0); in reset_controller()
326 lola_writel(chip, BAR1, DOINTCTL, val); in lola_irq_enable()
328 lola_writel(chip, BAR1, DIINTCTL, val); in lola_irq_enable()
333 lola_writel(chip, BAR1, DINTCTL, val); in lola_irq_enable()
338 lola_writel(chip, BAR1, DINTCTL, 0); in lola_irq_disable()
339 lola_writel(chip, BAR1, DIINTCT in lola_irq_disable()
[all...] |
| H A D | lola_proc.c | 171 snd_iprintf(buffer, "BAR1 %02x: %08x\n", i, in lola_proc_regs_read()
172 readl(chip->bar[BAR1].remap_addr + i)); in lola_proc_regs_read()
176 snd_iprintf(buffer, "BAR1 %02x: %08x\n", i, in lola_proc_regs_read()
177 readl(chip->bar[BAR1].remap_addr + i)); in lola_proc_regs_read()
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| /linux/drivers/misc/bcm-vk/ |
| H A D | bcm_vk.h | 198 * BAR1
201 /* BAR1 message q definition */
203 /* indicate if msgq ctrl in BAR1 is populated */
209 /* number of msgqs in BAR1 */
211 /* BAR1 queue control structure offset */
214 /* BAR1 ucode and boot1 version tag */
230 /* BAR1 DAUTH info */
241 /* BAR1 SOTP AUTH and REVID info */
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| /linux/Documentation/doc-guide/ |
| H A D | parse-headers.rst | 160 enum foo { BAR1, BAR2, PRIVATE };
164 replace symbol BAR1 :c:type:\`foo\`
170 enum foo { BAR1, BAR2, PRIVATE };
172 It will make the BAR1 and BAR2 enum symbols to cross reference the foo
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| /linux/Documentation/translations/it_IT/doc-guide/ |
| H A D | parse-headers.rst | 165 enum foo { BAR1, BAR2, PRIVATE };
169 replace symbol BAR1 :c:type:\`foo\`
175 enum foo { BAR1, BAR2, PRIVATE };
177 Genererà un riferimento ai valori BAR1 e BAR2 dal simbolo foo nel dominio C.
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| /linux/Documentation/translations/zh_CN/doc-guide/ |
| H A D | parse-headers.rst | 153 enum foo { BAR1, BAR2, PRIVATE };
157 replace symbol BAR1 :c:type:\`foo\`
163 enum foo { BAR1, BAR2, PRIVATE };
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| /linux/drivers/misc/rp1/ |
| H A D | rp1_pci.c | 45 void __iomem *bar1; member
52 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq)); in msix_cfg_set()
57 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); in msix_cfg_clr()
234 rp1->bar1 = pcim_iomap(pdev, 1, 0); in rp1_probe()
235 if (!rp1->bar1) { in rp1_probe()
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| /linux/arch/mips/pci/ |
| H A D | pci-octeon.c | 395 /* BAR1 hole */ in octeon_pci_initialize()
397 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ in octeon_pci_initialize()
400 ctl_status_2.s.bb1 = 1; /* BAR1 is big */ in octeon_pci_initialize()
546 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are in octeon_pci_initialize()
612 * with BAR0/BAR1 during these reads. in octeon_pci_setup()
631 /* BAR1 movable mappings set for identity mapping */ in octeon_pci_setup()
650 /* Devices go after BAR1 */ in octeon_pci_setup()
665 /* BAR1 movable regions contiguous to cover the swiotlb */ in octeon_pci_setup()
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| /linux/arch/mips/cavium-octeon/ |
| H A D | dma-octeon.c | 93 /* Anything in the BAR1 hole or above goes via BAR2 */ in octeon_big_phys_to_dma()
121 /* Anything not in the BAR1 range goes via BAR2 */ in octeon_small_phys_to_dma()
226 * memory past the BAR1 hole. in plat_swiotlb_setup()
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| /linux/drivers/scsi/aacraid/ |
| H A D | src.c | 621 iounmap(dev->regs.src.bar1); in aac_src_ioremap()
622 dev->regs.src.bar1 = NULL; in aac_src_ioremap()
627 dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2), in aac_src_ioremap()
630 if (dev->regs.src.bar1 == NULL) in aac_src_ioremap()
634 iounmap(dev->regs.src.bar1); in aac_src_ioremap()
635 dev->regs.src.bar1 = NULL; in aac_src_ioremap()
657 dev->regs.src.bar1 = in aac_srcv_ioremap()
660 if (dev->regs.src.bar1 == NULL) in aac_srcv_ioremap()
664 iounmap(dev->regs.src.bar1); in aac_srcv_ioremap()
665 dev->regs.src.bar1 = NULL; in aac_srcv_ioremap()
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| H A D | base.c | 291 * BAR1, and cannot be supported on systems where we're unable in nvkm_mmu_host()
292 * to map BAR1 with write-combining. in nvkm_mmu_host()
304 * done through BAR1. in nvkm_mmu_host()
352 /* Write-combined BAR1 access. */ in nvkm_mmu_vram()
359 /* Uncached BAR1 access. */ in nvkm_mmu_vram()
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| /linux/drivers/pci/endpoint/functions/ |
| H A D | pci-epf-ntb.c | 185 * | BAR1 | | | Doorbell 2 +---------+ | |
331 *| BAR1 | | | Doorbell 2 +---+ | |
434 *| BAR1 | | | Doorbell 2 +---------+ | |
712 *| BAR1 | | |SCRATCHPAD REGION | | BAR1 |
724 * Clear BAR1 of EP CONTROLLER 2 which contains the HOST2's peer scratchpad
725 * region. While BAR1 is the default peer scratchpad BAR, an NTB could have
757 *| BAR1 | | |SCRATCHPAD REGION | | BAR1 |
769 * Set BAR1 of EP CONTROLLER 2 which contains the HOST2's peer scratchpad
770 * region. While BAR1 is the default peer scratchpad BAR, an NTB could have
828 * | BAR1 | | |SCRATCHPAD REGION | | BAR1 |
[all …]
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