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/freebsd/crypto/openssl/doc/internal/man3/
H A Devp_md_get_number.pod40 Returns the internal dynamic number assigned to I<cipher>.
44 Returns the internal dynamic number assigned to the I<cipher>. This is only
49 Keturns the internal dynamic number assigned to I<kdf>.
53 Returns the internal dynamic number assigned to I<kem>.
57 Returns the internal dynamic number assigned to the I<exchange>.
61 Returns the internal dynamic number assigned to the I<keymgmt>.
65 Returns the internal dynamic number assigned to I<mac>.
69 Returns the internal dynamic number assigned to the I<md>. This is
74 Returns the internal dynamic number assigned to I<rand>.
78 Returns the internal dynamic number assigned to I<signature>.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-dma.dtsi34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
35 assigned-clock-rates = <60000000>;
52 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
53 assigned-clock-rates = <60000000>;
70 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
71 assigned-clock-rates = <60000000>;
88 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
89 assigned-clock-rates = <60000000>;
102 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
103 assigned-clock-rates = <80000000>;
[all …]
H A Dimx8ulp.dtsi237 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
238 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
304 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
305 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
306 assigned-clock-rates = <48000000>;
317 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
318 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
319 assigned-clock-rates = <48000000>;
350 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
351 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
[all …]
H A Dimx8mn-evk.dtsi308 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
309 assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
310 assigned-clock-rates = <24000000>;
334 assigned-clocks = <&clk IMX8MN_CLK_PDM>;
335 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
336 assigned-clock-rates = <196608000>;
377 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
378 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
379 assigned-clock-rates = <24576000>;
386 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
[all …]
H A Dimx8mp.dtsi737 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
747 assigned-clock-rates = <0>, <0>,
798 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
801 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
804 assigned-clock-rates = <800000000>,
814 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
816 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
818 assigned-clock-rates = <400000000>,
834 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
[all …]
H A Dimx8qxp-mek.dts224 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
228 assigned-clock-rates = <786432000>,
281 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
285 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
292 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
296 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
303 assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
308 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
309 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
315 assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti,phy-j721e-wiz.yaml95 assigned-clocks:
98 assigned-clock-parents:
104 - assigned-clocks
105 - assigned-clock-parents
131 assigned-clocks:
134 assigned-clock-parents:
140 - assigned-clocks
141 - assigned-clock-parents
210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned
[all...]
H A Dmixel,mipi-dsi-phy.yaml65 - assigned-clocks
66 - assigned-clock-parents
67 - assigned-clock-rates
76 assigned-clocks: false
77 assigned-clock-parents: false
78 assigned-clock-rates: false
93 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
94 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
95 assigned-clock-rates = <24000000>;
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra-audio-graph-card.yaml35 assigned-clocks:
39 assigned-clock-parents:
43 assigned-clock-rates:
63 - assigned-clocks
64 - assigned-clock-parents
79 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
82 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
83 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
101 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
102 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
[all …]
H A Dnvidia,tegra210-ahub.yaml43 assigned-clocks:
46 assigned-clock-parents:
49 assigned-clock-rates:
122 - assigned-clocks
123 - assigned-clock-parents
139 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
140 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
176 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
177 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
178 assigned-clock-rates = <1536000>;
[all …]
H A Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
H A Dnvidia,tegra210-dmic.yaml45 assigned-clocks:
48 assigned-clock-parents:
51 assigned-clock-rates:
79 - assigned-clocks
80 - assigned-clock-parents
93 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
94 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
95 assigned-clock-rates = <3072000>;
H A Dnvidia,tegra186-dspk.yaml45 assigned-clocks:
48 assigned-clock-parents:
51 assigned-clock-rates:
79 - assigned-clocks
80 - assigned-clock-parents
94 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
95 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
96 assigned-clock-rates = <12288000>;
H A Dnvidia,tegra210-i2s.yaml58 assigned-clocks:
62 assigned-clock-parents:
66 assigned-clock-rates:
95 - assigned-clocks
96 - assigned-clock-parents
109 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
110 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
111 assigned-clock-rates = <1536000>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
262 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
263 assigned
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j784s4-main.dtsi129 assigned-clocks = <&k3_clks 157 34>;
130 assigned-clock-parents = <&k3_clks 157 63>;
284 assigned-clocks = <&k3_clks 97 2>;
285 assigned-clock-parents = <&k3_clks 97 3>;
296 assigned-clocks = <&k3_clks 98 2>;
297 assigned-clock-parents = <&k3_clks 98 3>;
308 assigned-clocks = <&k3_clks 99 2>;
309 assigned-clock-parents = <&k3_clks 99 3>;
320 assigned-clocks = <&k3_clks 100 2>;
321 assigned-clock-parents = <&k3_clks 100 3>;
[all …]
H A Dk3-j784s4-mcu-wakeup.dtsi172 assigned-clocks = <&k3_clks 35 2>;
173 assigned-clock-parents = <&k3_clks 35 3>;
187 assigned-clocks = <&k3_clks 117 2>;
188 assigned-clock-parents = <&k3_clks 117 3>;
201 assigned-clocks = <&k3_clks 118 2>;
202 assigned-clock-parents = <&k3_clks 118 3>;
215 assigned-clocks = <&k3_clks 119 2>;
216 assigned-clock-parents = <&k3_clks 119 3>;
229 assigned-clocks = <&k3_clks 120 2>;
230 assigned-clock-parents = <&k3_clks 120 3>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi167 assigned-clocks = <&k3_clks 35 1>;
168 assigned-clock-parents = <&k3_clks 35 2>;
181 assigned-clocks = <&k3_clks 83 1>;
182 assigned-clock-parents = <&k3_clks 83 2>;
195 assigned-clocks = <&k3_clks 84 1>;
196 assigned-clock-parents = <&k3_clks 84 2>;
209 assigned-clocks = <&k3_clks 85 1>;
210 assigned-clock-parents = <&k3_clks 85 2>;
223 assigned-clocks = <&k3_clks 86 1>;
224 assigned-clock-parents = <&k3_clks 86 2>;
[all …]
H A Dk3-j721e-main.dtsi705 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
706 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
714 assigned-clocks = <&wiz0_pll0_refclk>;
715 assigned-clock-parents = <&k3_clks 292 11>;
721 assigned-clocks = <&wiz0_pll1_refclk>;
722 assigned-clock-parents = <&k3_clks 292 0>;
728 assigned-clocks = <&wiz0_refclk_dig>;
729 assigned-clock-parents = <&k3_clks 292 11>;
765 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
766 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi112 assigned-clocks = <&k3_clks 35 1>;
113 assigned-clock-parents = <&k3_clks 35 2>;
126 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
127 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
140 assigned-clocks = <&k3_clks 72 1>;
141 assigned-clock-parents = <&k3_clks 72 2>;
154 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
155 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
168 assigned-clocks = <&k3_clks 74 1>;
169 assigned-clock-parents = <&k3_clks 74 2>;
[all …]
H A Dk3-am62-main.dtsi67 assigned-clocks = <&k3_clks 157 0>;
68 assigned-clock-parents = <&k3_clks 157 8>;
76 assigned-clocks = <&k3_clks 157 10>;
77 assigned-clock-parents = <&k3_clks 157 18>;
255 assigned-clocks = <&k3_clks 36 2>;
256 assigned-clock-parents = <&k3_clks 36 3>;
267 assigned-clocks = <&k3_clks 37 2>;
268 assigned-clock-parents = <&k3_clks 37 3>;
279 assigned-clocks = <&k3_clks 38 2>;
280 assigned-clock-parents = <&k3_clks 38 3>;
[all …]
H A Dk3-am62a-main.dtsi67 assigned-clocks = <&k3_clks 157 0>;
68 assigned-clock-parents = <&k3_clks 157 8>;
76 assigned-clocks = <&k3_clks 157 10>;
77 assigned-clock-parents = <&k3_clks 157 18>;
282 assigned-clocks = <&k3_clks 36 2>;
283 assigned-clock-parents = <&k3_clks 36 3>;
294 assigned-clocks = <&k3_clks 37 2>;
295 assigned-clock-parents = <&k3_clks 37 3>;
306 assigned-clocks = <&k3_clks 38 2>;
307 assigned-clock-parents = <&k3_clks 38 3>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddpu.txt38 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
39 - assigned-clock-rates: list of clock frequencies sorted in the same order as
40 the assigned-clocks property.
70 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
71 - assigned-clock-rates: list of clock frequencies sorted in the same order as
72 the assigned-clocks property.
87 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88 assigned-clock-rates = <300000000>;
116 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
118 assigned-clock-rates = <0 0 300000000 19200000>;
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos4412-odroid-common.dtsi129 assigned-clocks = <&clock CLK_FOUT_EPLL>;
130 assigned-clock-rates = <45158401>;
134 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
140 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
143 assigned-clock-rates = <0>, <0>,
211 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
213 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
214 assigned-clock-rates = <0>, <176000000>;
219 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
221 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-clk-ccf.dtsi165 assigned-clocks = <&zynqmp_clk GEM_TSU>;
172 assigned-clocks = <&zynqmp_clk GEM_TSU>;
179 assigned-clocks = <&zynqmp_clk GEM_TSU>;
186 assigned-clocks = <&zynqmp_clk GEM_TSU>;
215 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
220 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
249 assigned-clocks = <&zynqmp_clk UART0_REF>;
254 assigned-clocks = <&zynqmp_clk UART1_REF>;
259 assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
268 assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
[all …]

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