Searched full:adjustable (Results 1 – 25 of 49) sorted by relevance
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49 This is adjustable via64 This is adjustable via83 This is adjustable via102 This is adjustable via120 This is adjustable via136 This is adjustable via
7 * Adjustable divider clock implementation16 * DOC: basic adjustable divider clock that cannot gate21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)32 * struct zynqmp_clk_divider - adjustable divider clock
13 * DOC: basic adjustable multiplexer clock that cannot gate19 * parent - parent is adjustable through clk_set_parent
5 * Adjustable factor-based clock implementation19 * DOC: basic adjustable factor-based clock24 * rate - rate is adjustable.
398 #define MWIFIEX_MEF_MAX_BYTESEQ 6 /* non-adjustable */446 #define MWIFIEX_COALESCE_MAX_BYTESEQ 4 /* non-adjustable */
22 this vlaue is adjustable depending on platform.
18 * DOC: basic adjustable multiplexer clock that cannot gate24 * parent - parent is adjustable through clk_set_parent
7 * Adjustable divider clock implementation20 * DOC: basic adjustable divider clock that cannot gate25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
16 * rate - rate is adjustable.22 * rate - rate is adjustable.28 * rate - rate is adjustable.
20 adjustable conversion time, and averaging function are also built in for
89 - FF_GAIN gain is adjustable90 - FF_AUTOCENTER autocenter is adjustable
24 Each vcpu has an adjustable guest_halt_poll_ns
29 temperature sensors. Each PWM output is individually adjustable and
26 board supply voltage and inrush current are ramped up at an adjustable rate. An
64 three temperature sensors. Each PWM output is individually adjustable and
200 __u32 dmode_extra; /* adjustable bus settings */201 __u32 dcntl_extra; /* adjustable bus settings */202 __u32 ctest7_extra; /* adjustable bus settings */
55 * struct imx_icc_node_adj - Describe a dynamic adjustable node
40 * struct sprd_pll - definition of adjustable pll clock
64 * struct clk_regmap_div_data - regmap backed adjustable divider specific data
20 tuners does not have much adjustable features.
20 * The clock is an adjustable fractional divider with a busy bit to wait
77 The current limit sense voltage of the chip is adjustable between
81 switches the physical clock back to normal, adjustable
41 * release 1.1, and then it's "adjustable" and probably not defaulted.