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/freebsd/sys/contrib/device-tree/src/riscv/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
146 compatible = "andestech,ax45mp-cache", "cache";
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml36 - andestech,ax45mp
H A Dextensions.yaml570 Registers in the AX45MP datasheet.
571 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
/freebsd/sys/riscv/riscv/
H A Dplic.c255 * least the Renesas RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) in plic_map_intr()